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    Searched refs:ZERO_EXTEND_VECTOR_INREG (Results 1 - 14 of 14) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ISDOpcodes.h 761 /// ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an
770 ZERO_EXTEND_VECTOR_INREG,
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
LegalizeVectorOps.cpp 124 /// Implement expansion for ZERO_EXTEND_VECTOR_INREG.
438 case ISD::ZERO_EXTEND_VECTOR_INREG:
748 case ISD::ZERO_EXTEND_VECTOR_INREG:
1064 "ZERO_EXTEND_VECTOR_INREG vector size mismatch");
SelectionDAGDumper.cpp 339 case ISD::ZERO_EXTEND_VECTOR_INREG: return "zero_extend_vector_inreg";
LegalizeVectorTypes.cpp 69 case ISD::ZERO_EXTEND_VECTOR_INREG:
422 case ISD::ZERO_EXTEND_VECTOR_INREG:
962 case ISD::ZERO_EXTEND_VECTOR_INREG:
2210 case ISD::ZERO_EXTEND_VECTOR_INREG:
3084 case ISD::ZERO_EXTEND_VECTOR_INREG:
3559 // operations should be done with SIGN/ZERO_EXTEND_VECTOR_INREG, which
3566 return DAG.getNode(ISD::ZERO_EXTEND_VECTOR_INREG, DL, WidenVT, InOp);
3691 case ISD::ZERO_EXTEND_VECTOR_INREG:
3709 case ISD::ZERO_EXTEND_VECTOR_INREG:
4664 return DAG.getNode(ISD::ZERO_EXTEND_VECTOR_INREG, DL, VT, InOp)
    [all...]
TargetLowering.cpp 807 case ISD::ZERO_EXTEND_VECTOR_INREG: {
1880 case ISD::ZERO_EXTEND_VECTOR_INREG: {
1885 bool IsVecInReg = Op.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG;
1959 IsVecInReg ? ISD::ZERO_EXTEND_VECTOR_INREG : ISD::ZERO_EXTEND;
2778 case ISD::ZERO_EXTEND_VECTOR_INREG: {
2796 if (Op.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG) {
DAGCombiner.cpp 1677 case ISD::ZERO_EXTEND_VECTOR_INREG: return visitEXTEND_VECTOR_INREG(N);
10257 Opcode == ISD::ZERO_EXTEND_VECTOR_INREG)
10309 Opcode == ISD::ZERO_EXTEND || Opcode == ISD::ZERO_EXTEND_VECTOR_INREG;
11848 N0.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG) {
11853 bool IsZext = N0.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG;
20561 // TODO Add support for ZERO_EXTEND_VECTOR_INREG when we have a test case.
20633 Opcode != ISD::ZERO_EXTEND_VECTOR_INREG)
LegalizeIntegerTypes.cpp 119 case ISD::ZERO_EXTEND_VECTOR_INREG:
4852 case ISD::ZERO_EXTEND_VECTOR_INREG:
SelectionDAG.cpp 3254 case ISD::ZERO_EXTEND_VECTOR_INREG: {
4932 case ISD::ZERO_EXTEND_VECTOR_INREG:
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonISelLoweringHVX.cpp 101 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, T, Legal);
164 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, T, Legal);
1646 return DAG.getNode(ISD::ZERO_EXTEND_VECTOR_INREG, SDLoc(Op), ty(Op),
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
TargetLoweringBase.cpp 812 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelLowering.cpp 1159 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Legal);
1380 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Custom);
1627 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Custom);
2040 setTargetDAGCombine(ISD::ZERO_EXTEND_VECTOR_INREG);
6342 case ISD::ZERO_EXTEND_VECTOR_INREG:
6358 case ISD::ZERO_EXTEND_VECTOR_INREG:
6359 return ISD::ZERO_EXTEND_VECTOR_INREG;
7889 case ISD::ZERO_EXTEND_VECTOR_INREG:
10009 IndicesVec = DAG.getNode(ISD::ZERO_EXTEND_VECTOR_INREG, SDLoc(IndicesVec),
23976 // Lowering for SIGN_EXTEND_VECTOR_INREG and ZERO_EXTEND_VECTOR_INREG
    [all...]
X86ISelDAGToDAG.cpp 1055 : ISD::ZERO_EXTEND_VECTOR_INREG;
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZISelLowering.cpp 382 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Custom);
5284 // Lower a ZERO_EXTEND_VECTOR_INREG to a vector shuffle with a zero vector.
5477 case ISD::ZERO_EXTEND_VECTOR_INREG:
5789 Opcode == ISD::ZERO_EXTEND_VECTOR_INREG ||
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 16927 SubOpcd0 == ISD::ZERO_EXTEND_VECTOR_INREG) &&
16929 SubOpcd1 == ISD::ZERO_EXTEND_VECTOR_INREG)) {

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