| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 1317 /// ZEXTLOAD loads the integer operand and zero extends it to a larger
1321 enum LoadExtType { NON_EXTLOAD = 0, EXTLOAD, SEXTLOAD, ZEXTLOAD };
1323 static const int LAST_LOADEXT_TYPE = ZEXTLOAD + 1;
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| BasicTTIImpl.h | 905 ((Opcode == Instruction::ZExt) ? ISD::ZEXTLOAD : ISD::SEXTLOAD);
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| SelectionDAGNodes.h | 2690 /// Returns true if the specified node is a ZEXTLOAD.
2693 cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
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| TargetLowering.h | 2548 LType = ISD::ZEXTLOAD;
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| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 696 case ISD::ZEXTLOAD: OS << ", zext"; break;
728 case ISD::ZEXTLOAD: OS << ", zext"; break;
765 case ISD::ZEXTLOAD: OS << ", zext"; break;
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| DAGCombiner.cpp | 5203 TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, ExtVT))) {
5204 // ZEXTLOAD will match without needing to change the size of the value being
5219 !TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, ExtVT))
5222 if (!TLI.shouldReduceLoadWidth(LoadN, ISD::ZEXTLOAD, ExtVT))
5343 isLegalNarrowLdSt(Load, ISD::ZEXTLOAD, ExtVT)) {
5345 // ZEXTLOAD is already small enough.
5346 if (Load->getExtensionType() == ISD::ZEXTLOAD &&
5617 if (TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT, LoadVT)) {
5629 ISD::ZEXTLOAD, MLoad->isExpandingLoad());
5753 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD i
[all...] |
| LegalizeDAG.cpp | 730 // load an i8. This trick is correct for ZEXTLOAD because the top 7
749 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
762 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
789 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
791 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), Chain, Ptr,
817 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
826 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), Chain, Ptr,
906 SDValue Result = DAG.getExtLoad(ISD::ZEXTLOAD, dl, ILoadVT, Chain,
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| TargetLowering.cpp | 997 // If this is a ZEXTLoad and we are looking at the loaded value.
3577 // ZEXTLOAD / SEXTLOAD
3578 if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
7570 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
7572 HiExtType = ISD::ZEXTLOAD;
7577 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
7592 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
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| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| R600ISelLowering.cpp | 48 // EXTLOAD should be the same as ZEXTLOAD. It is legal for some address
55 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
56 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Custom);
57 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Custom);
67 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i32, MVT::v2i1, Expand);
71 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i1, Expand);
1379 (LoadNode->getExtensionType() == ISD::ZEXTLOAD))) {
1534 // Ext = In.Flags.isSExt() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
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| AMDGPUISelLowering.cpp | 125 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, VT, Expand);
137 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
138 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Legal);
139 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Legal);
140 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand);
151 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i8, Expand);
154 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i8, Expand);
157 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i16, Expand);
160 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v3i16, Expand);
163 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i16, Expand)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 125 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
129 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Expand);
446 SDValue Low = DAG.getExtLoad(ISD::ZEXTLOAD, DL, MVT::i32, Chain, BasePtr,
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| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 142 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 1601 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand);
1662 setLoadExtAction(ISD::ZEXTLOAD, TargetVT, VT, Expand);
1681 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, MVT::v2i8, Legal);
1684 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, MVT::v4i8, Legal);
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| HexagonISelDAGToDAG.cpp | 77 bool IsZeroExt = (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD);
133 if (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD) {
285 IntExt = ISD::ZEXTLOAD;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelLowering.cpp | 267 for (auto Ext : {ISD::EXTLOAD, ISD::ZEXTLOAD, ISD::SEXTLOAD})
275 for (auto Ext : {ISD::EXTLOAD, ISD::ZEXTLOAD, ISD::SEXTLOAD})
281 for (auto Ext : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| LanaiISelLowering.cpp | 137 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 314 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
490 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom);
2712 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
2715 // (set dst, (i64 (zextload baseptr)))
4420 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(),
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| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 273 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
827 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
3526 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
3548 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
7188 ISD::ZEXTLOAD, dl, PtrVT, Chain,
8504 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::ZEXTLOAD)) {
13936 (LD->getExtensionType() != ISD::ZEXTLOAD &&
16110 LD->getExtensionType() == ISD::ZEXTLOAD))
17181 case ISD::ZEXTLOAD:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| AVRISelLowering.cpp | 60 for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 67 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZISelDAGToDAG.cpp | 1001 Load->getExtensionType() == ISD::ZEXTLOAD) &&
|
| SystemZISelLowering.cpp | 300 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
334 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
2120 } else if (Load->getExtensionType() == ISD::ZEXTLOAD) {
2131 ISD::ZEXTLOAD);
2162 case ISD::ZEXTLOAD:
2312 if ((Type == ISD::ZEXTLOAD && C.ICmpType != SystemZICMP::SignedOnly) ||
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 1443 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i32, Expand);
1447 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i32, VT, Expand);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVISelLowering.cpp | 166 for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD})
459 setLoadExtAction(ISD::ZEXTLOAD, OtherVT, VT, Expand);
534 setLoadExtAction(ISD::ZEXTLOAD, OtherVT, VT, Expand);
630 setLoadExtAction(ISD::ZEXTLOAD, OtherVT, VT, Expand);
923 LD->getExtensionType() == ISD::ZEXTLOAD))
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| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| M68kISelLowering.cpp | 64 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
|
