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    Searched refs:Zero64 (Results 1 - 5 of 5) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPULegalizerInfo.cpp 2893 auto Zero64 = B.buildConstant(S64, 0);
2894 auto NegDenom = B.buildSub(S64, Zero64, Denom);
SIInstrInfo.cpp 5331 Register Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
5337 // Zero64 = 0
5338 BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(AMDGPU::S_MOV_B64), Zero64)
5349 // NewSRsrc = {Zero64, SRsrcFormat}
5351 .addReg(Zero64)
AMDGPUISelLowering.cpp 1833 SDValue Zero64 = DAG.getConstant(0, DL, VT);
1838 SDValue Neg_RHS = DAG.getNode(ISD::SUB, DL, VT, Zero64, RHS);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
LegalizerHelper.cpp 5615 auto Zero64 = MIRBuilder.buildConstant(S64, 0);
5622 auto NotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, Src, Zero64);
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZISelLowering.cpp 7743 Register Zero64 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
7745 BuildMI(*MBB, MI, DL, TII->get(SystemZ::LLILL), Zero64)
7748 .addReg(In128).addReg(Zero64).addImm(SystemZ::subreg_h64);

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