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    Searched refs:ZeroReg (Results 1 - 22 of 22) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/Mips/
Target.cpp 74 unsigned ZeroReg;
77 ZeroReg = Mips::ZERO;
82 ZeroReg = Mips::ZERO_64;
91 .addReg(ZeroReg)
104 .addReg(ZeroReg)
123 .addReg(ZeroReg)
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86FixupSetCC.cpp 114 Register ZeroReg = MRI->createVirtualRegister(RC);
116 ZeroReg);
122 .addReg(ZeroReg)
X86FrameLowering.cpp 757 // ZeroReg = 0
760 // FinalReg = !Flags.Ovf ? TestReg : ZeroReg
800 ZeroReg = InProlog ? X86::RCX
860 BuildMI(&MBB, DL, TII.get(X86::XOR64rr), ZeroReg)
861 .addReg(ZeroReg, RegState::Undef)
862 .addReg(ZeroReg, RegState::Undef);
869 .addReg(ZeroReg)
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsSEInstrInfo.cpp 87 unsigned Opc = 0, ZeroReg = 0;
95 Opc = Mips::OR, ZeroReg = Mips::ZERO;
151 Opc = Mips::OR64, ZeroReg = Mips::ZERO_64;
182 if (ZeroReg)
183 MIB.addReg(ZeroReg);
626 unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
645 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg)
MipsSEISelDAGToDAG.cpp 85 unsigned DstReg = 0, ZeroReg = 0;
93 ZeroReg = Mips::ZERO;
99 ZeroReg = Mips::ZERO_64;
105 // Replace uses with ZeroReg.
119 if (!MRI->getRegClass(MO.getReg())->contains(ZeroReg))
122 MO.setReg(ZeroReg);
MipsAsmPrinter.cpp 144 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
145 TmpInst0.addOperand(MCOperand::createReg(ZeroReg));
  /src/external/gpl3/gcc.old/dist/libphobos/libdruntime/core/internal/
atomic.d 131 enum ZeroReg = SizedReg!(DX, T);
142 }, [SrcReg, ZeroReg, ResReg]));
150 enum ZeroReg = SizedReg!(DX, T);
162 }, [SrcReg, ZeroReg, ResReg]));
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMInstructionSelector.cpp 550 auto ZeroReg = MRI.createVirtualRegister(&ARM::GPRRegClass);
551 putConstant(I, ZeroReg, 0);
556 ZeroReg))
562 RHSReg, ZeroReg))
ARMFastISel.cpp 1473 unsigned ZeroReg = fastMaterializeConstant(Zero);
1476 .addReg(ZeroReg).addImm(1)
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
InstructionSelectorImpl.h 872 int64_t ZeroReg = MatchTable[CurrentIdx++];
876 OutMIs[NewInsnID].addReg(ZeroReg);
882 << OpIdx << ", " << ZeroReg << ")\n");
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64InstrInfo.h 162 bool KillSrc, unsigned Opcode, unsigned ZeroReg,
AArch64InstrInfo.cpp 3205 unsigned Opcode, unsigned ZeroReg,
3220 MIB.addReg(ZeroReg);
4504 unsigned CombineOpc, unsigned ZeroReg = 0,
4523 if (MI->getOperand(3).getReg() != ZeroReg)
4533 unsigned MulOpc, unsigned ZeroReg) {
4534 return canCombine(MBB, MO, MulOpc, ZeroReg, true);
4594 auto setFound = [&](int Opcode, int Operand, unsigned ZeroReg,
4596 if (canCombineWithMUL(MBB, Root.getOperand(Operand), Opcode, ZeroReg)) {
5250 unsigned BitSize, OrrOpc, ZeroReg;
5255 ZeroReg = AArch64::WZR
    [all...]
AArch64ExpandPseudoInsts.cpp 76 unsigned ExtendImm, unsigned ZeroReg,
186 unsigned StlrOp, unsigned CmpOp, unsigned ExtendImm, unsigned ZeroReg,
219 BuildMI(LoadCmpBB, DL, TII->get(CmpOp), ZeroReg)
AArch64FastISel.cpp 380 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
383 ResultReg).addReg(ZeroReg, getKillRegState(true));
4845 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
4848 ResultReg = emitAddSub_rs(/*UseAdd=*/false, VT, ZeroReg, SelectReg,
AArch64ISelDAGToDAG.cpp 2805 unsigned ZeroReg;
2809 ZeroReg = AArch64::WZR;
2813 ZeroReg = AArch64::XZR;
2816 CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, ZeroReg, SubVT);
AArch64ISelLowering.cpp 14429 unsigned ZeroReg;
14432 ZeroReg = AArch64::WZR;
14435 ZeroReg = AArch64::XZR;
14439 DAG.getCopyFromReg(DAG.getEntryNode(), DL, ZeroReg, ZeroVT);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/
MipsAsmParser.cpp 2721 unsigned ZeroReg = IsAddress ? ABI.GetNullPtr() : ABI.GetZeroReg();
2741 SrcReg = ZeroReg;
2763 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, ImmValue, IDLoc, STI);
2787 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits31To16, IDLoc, STI);
2816 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits, IDLoc, STI);
4189 unsigned ZeroReg;
4194 ZeroReg = Mips::ZERO_64;
4198 ZeroReg = Mips::ZERO;
4222 TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
CombinerHelper.cpp 2160 Register ZeroReg;
2162 if (!ZeroReg)
2163 ZeroReg = Builder.buildConstant(Dst0Ty, 0).getReg(0);
2164 replaceRegWith(MRI, MI.getOperand(Idx).getReg(), ZeroReg);
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCInstrInfo.cpp 2091 MCRegister ZeroReg;
2094 ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
2096 ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
2100 UseMI.getOperand(UseIdx).setReg(ZeroReg);
PPCISelLowering.cpp 11191 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
11258 if (ptrA != ZeroReg) {
11303 .addReg(ZeroReg)
11347 .addReg(ZeroReg)
12238 Register ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
12271 if (ptrA != ZeroReg) {
12328 .addReg(ZeroReg)
12352 .addReg(ZeroReg)
12365 .addReg(ZeroReg)
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64InstructionSelector.cpp 4252 const Register ZeroReg = AArch64::WZR;
4255 MIRBuilder.buildInstr(AArch64::CSINCWr, {CsetDst}, {ZeroReg, ZeroReg})
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIInstrInfo.cpp 7227 Register ZeroReg = MRI.createVirtualRegister(RI.getBoolRC());
7229 ZeroReg, 0);
7230 HeaderPHIBuilder.addReg(ZeroReg);

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