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    Searched refs:_MASKED_BIT_ENABLE (Results 1 - 17 of 17) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/i915/gvt/
mmio_context.h 59 (_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT) == \
60 ((a) & _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT)))
handlers.c 1721 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(1);
1723 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(2);
1726 if (data & _MASKED_BIT_ENABLE(1)) {
1732 data & _MASKED_BIT_ENABLE(2)) {
1741 if (((data & _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)) ||
1742 (data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)))
1747 if ((data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE))
1809 if (data & _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET))
1824 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(0x18);
1827 if (data & _MASKED_BIT_ENABLE(0x10) || data & _MASKED_BIT_ENABLE(0x8)
    [all...]
mmio_context.c 466 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
  /src/sys/external/bsd/drm2/dist/drm/i915/gt/
intel_ring_submission.c 593 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
617 RING_MI_MODE, _MASKED_BIT_ENABLE(STOP_RING));
877 _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE));
882 _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
892 _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
898 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
903 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
904 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
918 _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1399 *cs++ = _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE)
    [all...]
intel_rc6.c 363 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
388 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
676 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
686 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
gen6_ppgtt.c 59 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
85 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
intel_workarounds.c 180 wa_write_masked_or(wal, reg, val, _MASKED_BIT_ENABLE(val));
196 wa_write_masked_or(wal, (addr), (mask), _MASKED_BIT_ENABLE(mask))
570 _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE));
intel_reset.c 521 intel_uncore_write_fw(uncore, reg, _MASKED_BIT_ENABLE(request));
intel_engine_cs.c 891 intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING));
intel_lrc.c 3425 mode = _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE);
3427 mode = _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE);
4499 ctl = _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH);
  /src/sys/external/bsd/drm2/dist/drm/i915/
intel_pm.c 375 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
386 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
6414 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6482 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6525 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6533 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6643 _MASKED_BIT_ENABLE(GEN11_ENABLE_32_PLANE_MODE));
6694 _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
6791 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6820 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE))
    [all...]
i915_gem_fence_reg.c 906 _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
910 _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
914 _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
intel_uncore.c 114 _MASKED_BIT_ENABLE(val));
124 #define fw_set(d, val) writel(_MASKED_BIT_ENABLE((val)), (d)->reg_set)
i915_perf.c 2549 _MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
2582 _MASKED_BIT_ENABLE(GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
4134 val = val & ~_MASKED_BIT_ENABLE(GEN8_ST_PO_DISABLE);
4141 val = val & ~_MASKED_BIT_ENABLE(HSW_WAIT_FOR_RC6_EXIT_ENABLE);
i915_irq.c 2559 I915_WRITE(SCPD0, _MASKED_BIT_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));
i915_reg.h 278 #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
  /src/sys/external/bsd/drm2/dist/drm/i915/gt/uc/
intel_uc_fw.c 470 _MASKED_BIT_ENABLE(dma_flags | START_DMA));

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