| /src/sys/arch/news68k/include/ |
| pmap.h | 19 __SHIFTIN(0x1f,TT30_LAM) | \
21 __SHIFTIN(4,TT30_FCBASE) | \
22 __SHIFTIN(3,TT30_FCMASK))
25 __SHIFTIN(0x1f,TT30_LAM) | \
27 __SHIFTIN(4,TT30_FCBASE) | \
28 __SHIFTIN(3,TT30_FCMASK))
|
| /src/sys/arch/luna68k/include/ |
| pmap.h | 19 __SHIFTIN(0x3f,TT30_LAM) | \
21 __SHIFTIN(4,TT30_FCBASE) | \
22 __SHIFTIN(3,TT30_FCMASK))
24 __SHIFTIN(0x7f,TT30_LAM) | \
26 __SHIFTIN(4,TT30_FCBASE) | \
27 __SHIFTIN(3,TT30_FCMASK))
30 __SHIFTIN(0x3f,TTR40_LAM) | \
34 __SHIFTIN(0x7f,TTR40_LAM) | \
|
| /src/sys/dev/ic/ |
| max2820reg.h | 115 #define MAX2820_SYNTH_R_22MHZ __SHIFTIN(0, MAX2820_SYNTH_R_MASK)
116 #define MAX2820_SYNTH_R_44MHZ __SHIFTIN(1, MAX2820_SYNTH_R_MASK)
118 #define MAX2820_SYNTH_R_DEFAULT __SHIFTIN(0, MAX2820_SYNTH_R_MASK)
125 #define MAX2820_CHANNEL_RSVD_DEFAULT __SHIFTIN(0, MAX2820_CHANNEL_RSVD)
126 #define MAX2820_CHANNEL_CF_DEFAULT __SHIFTIN(37, MAX2820_CHANNEL_CF_MASK)
152 #define MAX2820_RECEIVE_BW_8_5MHZ __SHIFTIN(0, MAX2820_RECEIVE_BW_MASK)
153 #define MAX2820_RECEIVE_BW_8MHZ __SHIFTIN(1, MAX2820_RECEIVE_BW_MASK)
154 #define MAX2820_RECEIVE_BW_7_5MHZ __SHIFTIN(2, MAX2820_RECEIVE_BW_MASK)
155 #define MAX2820_RECEIVE_BW_7MHZ __SHIFTIN(3, MAX2820_RECEIVE_BW_MASK)
156 #define MAX2820_RECEIVE_BW_6_5MHZ __SHIFTIN(4, MAX2820_RECEIVE_BW_MASK
[all...] |
| hfa3861areg.h | 44 #define HFA3861A_CR5_RATE_1 __SHIFTIN(0, HFA3861A_CR5_RATE_MASK)
45 #define HFA3861A_CR5_RATE_2 __SHIFTIN(1, HFA3861A_CR5_RATE_MASK)
46 #define HFA3861A_CR5_RATE_5 __SHIFTIN(2, HFA3861A_CR5_RATE_MASK)
47 #define HFA3861A_CR5_RATE_11 __SHIFTIN(3, HFA3861A_CR5_RATE_MASK)
70 #define HFA3861A_CR63_SIGNAL_1MBPS __SHIFTIN(0, HFA3861A_CR63_SIGNAL)
72 #define HFA3861A_CR63_SIGNAL_2MBPS __SHIFTIN(2, HFA3861A_CR63_SIGNAL)
74 #define HFA3861A_CR63_SIGNAL_OTHER_MBPS __SHIFTIN(1, HFA3861A_CR63_SIGNAL)
|
| sa2400reg.h | 61 #define SA2400_SYNB_L_INACTIVE0 __SHIFTIN(0, SA2400_SYNB_L_MASK)
62 #define SA2400_SYNB_L_INACTIVE1 __SHIFTIN(1, SA2400_SYNB_L_MASK)
63 #define SA2400_SYNB_L_NORMAL __SHIFTIN(2, SA2400_SYNB_L_MASK)
64 #define SA2400_SYNB_L_INACTIVE2 __SHIFTIN(3, SA2400_SYNB_L_MASK)
81 #define SA2400_SYNC_CP_NORMAL_ __SHIFTIN(0, SA2400_SYNC_CP_MASK)
82 #define SA2400_SYNC_CP_THIRD_ __SHIFTIN(1, SA2400_SYNC_CP_MASK)
83 #define SA2400_SYNC_CP_NORMAL __SHIFTIN(2, SA2400_SYNC_CP_MASK) /* recommended */
84 #define SA2400_SYNC_CP_THIRD __SHIFTIN(3, SA2400_SYNC_CP_MASK)
144 #define SA2400_OPMODE_MODE_SLEEP __SHIFTIN(0, SA2400_OPMODE_MODE_MASK)
145 #define SA2400_OPMODE_MODE_TXRX __SHIFTIN(1, SA2400_OPMODE_MODE_MASK
[all...] |
| rtwreg.h | 63 #define RTW_BRSR_MBR8180_1MBPS __SHIFTIN(0, RTW_BRSR_MBR8180_MASK)
64 #define RTW_BRSR_MBR8180_2MBPS __SHIFTIN(1, RTW_BRSR_MBR8180_MASK)
65 #define RTW_BRSR_MBR8180_5MBPS __SHIFTIN(2, RTW_BRSR_MBR8180_MASK)
66 #define RTW_BRSR_MBR8180_11MBPS __SHIFTIN(3, RTW_BRSR_MBR8180_MASK)
158 #define RTW_TCR_HWVERID_D __SHIFTIN(26, RTW_TCR_HWVERID_MASK)
159 #define RTW_TCR_HWVERID_F __SHIFTIN(27, RTW_TCR_HWVERID_MASK)
169 #define RTW_TCR_MXDMA_16 __SHIFTIN(0, RTW_TCR_MXDMA_MASK)
170 #define RTW_TCR_MXDMA_32 __SHIFTIN(1, RTW_TCR_MXDMA_MASK)
171 #define RTW_TCR_MXDMA_64 __SHIFTIN(2, RTW_TCR_MXDMA_MASK)
172 #define RTW_TCR_MXDMA_128 __SHIFTIN(3, RTW_TCR_MXDMA_MASK
[all...] |
| si4136reg.h | 46 #define SI4126_MAIN_AUXSEL_RSVD __SHIFTIN(0x0, SI4126_MAIN_AUXSEL_MASK)
48 #define SI4126_MAIN_AUXSEL_FRCLOW __SHIFTIN(0x1, SI4126_MAIN_AUXSEL_MASK)
50 #define SI4126_MAIN_AUXSEL_LDETB __SHIFTIN(0x3, SI4126_MAIN_AUXSEL_MASK)
|
| atwreg.h | 149 #define ATW_PAR_CAL_8DW __SHIFTIN(0x1, ATW_PAR_CAL_MASK)
151 #define ATW_PAR_CAL_16DW __SHIFTIN(0x2, ATW_PAR_CAL_MASK)
153 #define ATW_PAR_CAL_32DW __SHIFTIN(0x3, ATW_PAR_CAL_MASK)
156 #define ATW_PAR_PBL_1DW __SHIFTIN(0x1, ATW_PAR_PBL_MASK)
157 #define ATW_PAR_PBL_2DW __SHIFTIN(0x2, ATW_PAR_PBL_MASK)
158 #define ATW_PAR_PBL_4DW __SHIFTIN(0x4, ATW_PAR_PBL_MASK)
159 #define ATW_PAR_PBL_8DW __SHIFTIN(0x8, ATW_PAR_PBL_MASK)
160 #define ATW_PAR_PBL_16DW __SHIFTIN(0x16, ATW_PAR_PBL_MASK)
161 #define ATW_PAR_PBL_32DW __SHIFTIN(0x32, ATW_PAR_PBL_MASK)
272 #define ATW_NAR_TR_L64 __SHIFTIN(0x0, ATW_NAR_TR_MASK
[all...] |
| /src/sys/arch/mips/cavium/dev/ |
| octeon_pkovar.h | 96 __SHIFTIN(sz1, PKO_CMD_WORD0_SZ1) |
97 __SHIFTIN(sz0, PKO_CMD_WORD0_SZ0) |
98 __SHIFTIN(s1, PKO_CMD_WORD0_S1) |
99 __SHIFTIN(reg1, PKO_CMD_WORD0_REG1) |
100 __SHIFTIN(s0, PKO_CMD_WORD0_S0) |
101 __SHIFTIN(reg0, PKO_CMD_WORD0_REG0) |
102 __SHIFTIN(le, PKO_CMD_WORD0_LE) |
103 __SHIFTIN(n2, PKO_CMD_WORD0_N2) |
104 __SHIFTIN(q, PKO_CMD_WORD0_Q) |
105 __SHIFTIN(r, PKO_CMD_WORD0_R)
[all...] |
| /src/sys/arch/aarch64/include/ |
| pte.h | 53 #define LX_TBL_APTABLE_NOEFFECT __SHIFTIN(0,LX_TBL_APTABLE)
54 #define LX_TBL_APTABLE_EL0_NOACCESS __SHIFTIN(1,LX_TBL_APTABLE)
55 #define LX_TBL_APTABLE_RO __SHIFTIN(2,LX_TBL_APTABLE)
56 #define LX_TBL_APTABLE_RO_EL0_NOREAD __SHIFTIN(3,LX_TBL_APTABLE)
60 #define LX_BLKPAG_OS_0 __SHIFTIN(1,LX_BLKPAG_OS)
61 #define LX_BLKPAG_OS_1 __SHIFTIN(2,LX_BLKPAG_OS)
62 #define LX_BLKPAG_OS_2 __SHIFTIN(4,LX_BLKPAG_OS)
63 #define LX_BLKPAG_OS_3 __SHIFTIN(8,LX_BLKPAG_OS)
74 #define LX_BLKPAG_SH_NS __SHIFTIN(0,LX_BLKPAG_SH) /* Non Shareable */
75 #define LX_BLKPAG_SH_OS __SHIFTIN(2,LX_BLKPAG_SH) /* Outer Shareable *
[all...] |
| /src/sys/arch/m68k/include/ |
| mmu_30.h | 86 #define TT30_USERD __SHIFTIN(FC_USERD,TT30_FCBASE)
87 #define TT30_USERP __SHIFTIN(FC_USERP,TT30_FCBASE)
88 #define TT30_SUPERD __SHIFTIN(FC_SUPERD,TT30_FCBASE)
89 #define TT30_SUPERP __SHIFTIN(FC_SUPERP,TT30_FCBASE)
|
| mmu_40.h | 110 #define UTE40_INVALID __SHIFTIN(0, UTE_UDT)
111 #define UTE40_RESIDENT __SHIFTIN(2, UTE_UDT)
150 #define PTE40_CM_WT __SHIFTIN(0, PTE40_CM)
151 #define PTE40_CM_CB __SHIFTIN(1, PTE40_CM)
152 #define PTE40_CM_NC_SER __SHIFTIN(2, PTE40_CM)
153 #define PTE40_CM_NC __SHIFTIN(3, PTE40_CM)
155 #define PTE40_INVALID __SHIFTIN(0, PTE40_PDT)
156 #define PTE40_RESIDENT __SHIFTIN(1, PTE40_PDT)
157 #define PTE40_INDIRECT __SHIFTIN(2, PTE40_PDT)
193 #define TTR40_USER __SHIFTIN(0, TTR40_SFIELD
[all...] |
| mmu_51.h | 226 #define TCR51_PS_256 __SHIFTIN(0x8, TCR51_PS)
227 #define TCR51_PS_512 __SHIFTIN(0x9, TCR51_PS)
228 #define TCR51_PS_1K __SHIFTIN(0xa, TCR51_PS)
229 #define TCR51_PS_2K __SHIFTIN(0xb, TCR51_PS)
230 #define TCR51_PS_4K __SHIFTIN(0xc, TCR51_PS)
231 #define TCR51_PS_8K __SHIFTIN(0xd, TCR51_PS)
232 #define TCR51_PS_16K __SHIFTIN(0xe, TCR51_PS)
233 #define TCR51_PS_32K __SHIFTIN(0xf, TCR51_PS)
|
| /src/sys/arch/arm/samsung/ |
| sscom_reg.h | 46 #define ULCON_PARITY_NONE __SHIFTIN(0, ULCON_PARITY)
47 #define ULCON_PARITY_ODD __SHIFTIN(4, ULCON_PARITY)
48 #define ULCON_PARITY_EVEN __SHIFTIN(5, ULCON_PARITY)
49 #define ULCON_PARITY_ONE __SHIFTIN(6, ULCON_PARITY)
50 #define ULCON_PARITY_ZERO __SHIFTIN(7, ULCON_PARITY)
59 #define UCON_TXDMA_BRST_1 __SHIFTIN(0, UCON_TXDMA)
60 #define UCON_TXDMA_BRST_4 __SHIFTIN(1, UCON_TXDMA)
61 #define UCON_TXDMA_BRST_8 __SHIFTIN(2, UCON_TXDMA)
62 #define UCON_TXDMA_BRST_16 __SHIFTIN(3, UCON_TXDMA)
64 #define UCON_RXDMA_BRST_1 __SHIFTIN(0, UCON_RXDMA
[all...] |
| /src/sys/arch/arm/xilinx/ |
| zynq_uartreg.h | 45 #define NBSTOP_1 __SHIFTIN(0, MR_NBSTOP)
46 #define NBSTOP_15 __SHIFTIN(1, MR_NBSTOP)
47 #define NBSTOP_2 __SHIFTIN(2, MR_NBSTOP)
49 #define PAR_EVEN __SHIFTIN(0, MR_PAR)
50 #define PAR_ODD __SHIFTIN(1, MR_PAR)
51 #define PAR_ZERO __SHIFTIN(2, MR_PAR)
52 #define PAR_ONE __SHIFTIN(3, MR_PAR)
53 #define PAR_NONE __SHIFTIN(4, MR_PAR)
55 #define CHRL_6BIT __SHIFTIN(3, MR_CHRL)
56 #define CHRL_7BIT __SHIFTIN(2, MR_CHRL
[all...] |
| zynq_usbreg.h | 92 #define USBMODE_CM_IDLE __SHIFTIN(0, USBMODE_CM)
93 #define USBMODE_CM_DEVICE __SHIFTIN(2, USBMODE_CM)
94 #define USBMODE_CM_HOST __SHIFTIN(3, USBMODE_CM)
100 #define PORTSC_PTS_UTMI __SHIFTIN(0, PORTSC_PTS)
101 #define PORTSC_PTS_PHILIPS __SHIFTIN(1, PORTSC_PTS)
102 #define PORTSC_PTS_ULPI __SHIFTIN(2, PORTSC_PTS)
103 #define PORTSC_PTS_SERIAL __SHIFTIN(3, PORTSC_PTS)
|
| /src/sys/arch/i386/pci/ |
| geodereg.h | 69 #define SC1100_WDCNFG_WDTYPE2_NOACTION __SHIFTIN(0, SC1100_WDCNFG_WDTYPE2_MASK)
70 #define SC1100_WDCNFG_WDTYPE2_INTERRUPT __SHIFTIN(1, SC1100_WDCNFG_WDTYPE2_MASK)
71 #define SC1100_WDCNFG_WDTYPE2_SMI __SHIFTIN(2, SC1100_WDCNFG_WDTYPE2_MASK)
72 #define SC1100_WDCNFG_WDTYPE2_RESET __SHIFTIN(3, SC1100_WDCNFG_WDTYPE2_MASK)
74 #define SC1100_WDCNFG_WDTYPE1_NOACTION __SHIFTIN(0, SC1100_WDCNFG_WDTYPE1_MASK)
75 #define SC1100_WDCNFG_WDTYPE1_INTERRUPT __SHIFTIN(1, SC1100_WDCNFG_WDTYPE1_MASK)
76 #define SC1100_WDCNFG_WDTYPE1_SMI __SHIFTIN(2, SC1100_WDCNFG_WDTYPE1_MASK)
77 #define SC1100_WDCNFG_WDTYPE1_RESET __SHIFTIN(3, SC1100_WDCNFG_WDTYPE1_MASK)
|
| elan520reg.h | 67 #define MMCR_DBCTL_WB_WM_28DW __SHIFTIN(0, MMCR_DBCTL_WB_WM_MASK)
68 #define MMCR_DBCTL_WB_WM_24DW __SHIFTIN(1, MMCR_DBCTL_WB_WM_MASK)
69 #define MMCR_DBCTL_WB_WM_16DW __SHIFTIN(2, MMCR_DBCTL_WB_WM_MASK)
70 #define MMCR_DBCTL_WB_WM_8DW __SHIFTIN(3, MMCR_DBCTL_WB_WM_MASK)
78 __SHIFTIN(0, MMCR_HBCTL_T_DLYTR_ENB_MASK)
80 __SHIFTIN(1, MMCR_HBCTL_T_DLYTR_ENB_MASK)
82 __SHIFTIN(2, MMCR_HBCTL_T_DLYTR_ENB_MASK)
84 __SHIFTIN(3, MMCR_HBCTL_T_DLYTR_ENB_MASK)
237 #define MMCR_WPVSTA_WPV_MSTR_CPU __SHIFTIN(0, MMCR_WPVSTA_WPV_MSTR)
238 #define MMCR_WPVSTA_WPV_MSTR_PCI __SHIFTIN(1, MMCR_WPVSTA_WPV_MSTR
[all...] |
| /src/sys/dev/cadence/ |
| cemacreg.h | 142 #define ETH_CFG_CLK_8 __SHIFTIN(0, ETH_CFG_CLK)
143 #define ETH_CFG_CLK_16 __SHIFTIN(1, ETH_CFG_CLK)
144 #define ETH_CFG_CLK_32 __SHIFTIN(2, ETH_CFG_CLK)
145 #define ETH_CFG_CLK_64 __SHIFTIN(3, ETH_CFG_CLK)
158 #define GEM_CFG_CLK_8 __SHIFTIN(0, GEM_CFG_CLK)
159 #define GEM_CFG_CLK_16 __SHIFTIN(1, GEM_CFG_CLK)
160 #define GEM_CFG_CLK_32 __SHIFTIN(2, GEM_CFG_CLK)
161 #define GEM_CFG_CLK_48 __SHIFTIN(3, GEM_CFG_CLK)
162 #define GEM_CFG_CLK_64 __SHIFTIN(4, GEM_CFG_CLK)
163 #define GEM_CFG_CLK_96 __SHIFTIN(5, GEM_CFG_CLK
[all...] |
| /src/sys/arch/arm/amlogic/ |
| mesong12_usb2phy.c | 210 __SHIFTIN(1, USB2PHY_R16_USB2_MPLL_LOCK_LONG) |
212 __SHIFTIN(1, USB2PHY_R16_USB2_MPLL_N) |
213 __SHIFTIN(20, USB2PHY_R16_USB2_MPLL_M));
215 __SHIFTIN(0, USB2PHY_R17_USB2_MPLL_FILTER_PVT1) |
216 __SHIFTIN(7, USB2PHY_R17_USB2_MPLL_FILTER_PVT2) |
217 __SHIFTIN(7, USB2PHY_R17_USB2_MPLL_LAMBDA0) |
218 __SHIFTIN(2, USB2PHY_R17_USB2_MPLL_LAMBDA1) |
219 __SHIFTIN(9, USB2PHY_R17_USB2_MPLL_FRAC_IN));
222 __SHIFTIN(1, USB2PHY_R18_USB2_MPLL_ADJ_LDO) |
223 __SHIFTIN(3, USB2PHY_R18_USB2_MPLL_ALPHA)
[all...] |
| /src/sys/arch/x86/include/ |
| i82489reg.h | 85 #define LAPIC_DLMODE_FIXED __SHIFTIN(0, LAPIC_DLMODE_MASK)
86 #define LAPIC_DLMODE_LOW __SHIFTIN(1, LAPIC_DLMODE_MASK) /* NA in x2APIC */
87 #define LAPIC_DLMODE_SMI __SHIFTIN(2, LAPIC_DLMODE_MASK)
88 #define LAPIC_DLMODE_NMI __SHIFTIN(4, LAPIC_DLMODE_MASK)
89 #define LAPIC_DLMODE_INIT __SHIFTIN(5, LAPIC_DLMODE_MASK)
90 #define LAPIC_DLMODE_STARTUP __SHIFTIN(6, LAPIC_DLMODE_MASK) /* NA in LVT,MSI*/
91 #define LAPIC_DLMODE_EXTINT __SHIFTIN(7, LAPIC_DLMODE_MASK) /* NA in x2APIC */
111 # define LAPIC_DSTMODE_PHYS __SHIFTIN(0, LAPIC_DSTMODE_MASK)
112 # define LAPIC_DSTMODE_LOG __SHIFTIN(1, LAPIC_DSTMODE_MASK)
115 # define LAPIC_DEST_DEFAULT __SHIFTIN(0, LAPIC_DEST_MASK
[all...] |
| /src/sys/arch/next68k/include/ |
| pmap.h | 22 __SHIFTIN(0x03,TTR40_LAM) | \
|
| /src/sys/arch/mac68k/include/ |
| pmap.h | 17 __SHIFTIN(0xff,TT30_LAM) | \
|
| /src/sys/arch/arm/imx/ |
| imxusbreg.h | 89 #define USBMODE_CM_IDLE __SHIFTIN(0,USBMODE_CM)
90 #define USBMODE_CM_DEVICE __SHIFTIN(2,USBMODE_CM)
91 #define USBMODE_CM_HOST __SHIFTIN(3,USBMODE_CM)
98 #define PORTSC_PTS_UTMI __SHIFTIN(0,PORTSC_PTS)
99 #define PORTSC_PTS_PHILIPS __SHIFTIN(1,PORTSC_PTS) /* not in i.MX51*/
100 #define PORTSC_PTS_ULPI __SHIFTIN(2,PORTSC_PTS)
101 #define PORTSC_PTS_SERIAL __SHIFTIN(3,PORTSC_PTS)
|
| /src/sys/arch/arm/include/ |
| fenv.h | 49 *(__envp) = __SHIFTIN((__val), VFP_FPSCR_CSUM)
51 *(__envp) = __SHIFTIN((__val), VFP_FPSCR_ESUM)
53 *(__envp) = __SHIFTIN((__val), VFP_FPSCR_RMODE)
|
