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    Searched refs:__mask (Results 1 - 12 of 12) sorted by relevancy

  /src/include/
fenv.h 61 int __mask; member in struct:__anona11aeb850108
66 #define __FENV_GET_MASK(__envp) (__envp)->__mask
71 (__envp)->__mask = (__val)
  /src/sys/arch/riscv/include/
sysreg.h 128 csr_##regname##_set(uintptr_t __mask) \
130 if (__builtin_constant_p(__mask) && __mask < 0x20) { \
131 asm volatile("csrsi " #regname ", %0" :: "i"(__mask) : \
134 asm volatile("csrs " #regname ", %0" :: "r"(__mask) : \
141 csr_##regname##_clear(uintptr_t __mask) \
143 if (__builtin_constant_p(__mask) && __mask < 0x20) { \
144 asm volatile("csrci " #regname ", %0" :: "i"(__mask) : \
147 asm volatile("csrc " #regname ", %0" :: "r"(__mask) :
    [all...]
  /src/sys/arch/arm/include/
asm.h 85 #define __LOWEST_SET_BIT(__mask) ((((__mask) - 1) & (__mask)) ^ (__mask))
86 #define __SHIFTOUT(__x, __mask) (((__x) & (__mask)) / __LOWEST_SET_BIT(__mask))
87 #define __SHIFTIN(__x, __mask) ((__x) * __LOWEST_SET_BIT(__mask))
  /src/sys/sys/
cdefs.h 662 /* __MASK(n): first n bits all set, where __MASK(4) == 0b1111. */
663 #define __MASK(__n) (__BIT(__n) - 1)
675 #define __LOWEST_SET_BIT(__mask) ((((__mask) - 1) & (__mask)) ^ (__mask))
683 #define __SHIFTOUT(__x, __mask) (((__x) & (__mask)) / __LOWEST_SET_BIT(__mask))
    [all...]
  /src/sys/arch/ia64/include/
fenv.h 222 feenableexcept(int __mask)
227 __newfpsr = __oldfpsr & ~(__mask & FE_ALL_EXCEPT);
233 fedisableexcept(int __mask)
238 __newfpsr = __oldfpsr | (__mask & FE_ALL_EXCEPT);
  /src/sys/arch/sh3/include/
fenv.h 258 feenableexcept(int __mask)
264 __fpscr |= (__mask & FE_ALL_EXCEPT) << 5;
271 fedisableexcept(int __mask)
277 __fpscr &= ~(__mask & FE_ALL_EXCEPT) << 5;
  /src/sys/external/bsd/drm2/dist/drm/i2c/
ch7006_priv.h 144 #define __mask(src, bitfield) \ macro
146 #define mask(bitfield) __mask(bitfield)
149 (((x) >> (src) << (0 ? bitfield)) & __mask(src, bitfield))
157 ((x & __mask(src, bitfield)) >> (0 ? bitfield) << (src))
  /src/sys/arch/m68k/include/
fenv.h 276 feenableexcept(int __mask)
282 __fpcr |= (__mask & FE_ALL_EXCEPT) << 6;
289 fedisableexcept(int __mask)
295 __fpcr &= ~((__mask & FE_ALL_EXCEPT) << 6);
  /src/sys/arch/powerpc/include/
fenv.h 289 feenableexcept(int __mask)
296 __r.__bits.__reg |= (__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT;
303 fedisableexcept(int __mask)
310 __r.__bits.__reg &= ~((__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT);
  /src/sys/arch/mips/include/
asm.h 69 #define __LOWEST_SET_BIT(__mask) ((((__mask) - 1) & (__mask)) ^ (__mask))
70 #define __SHIFTOUT(__x, __mask) (((__x) & (__mask)) / __LOWEST_SET_BIT(__mask))
71 #define __SHIFTIN(__x, __mask) ((__x) * __LOWEST_SET_BIT(__mask))
  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_display.h 339 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
341 for_each_if((__mask) & BIT(__p))
343 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
345 for_each_if ((__mask) & (1 << (__t)))
  /src/sys/external/bsd/drm2/dist/drm/i915/
i915_reg.h 157 * @__mask: shifted mask defining the field's length and position
163 * @return: @__val masked and shifted into the field defined by @__mask.
165 #define REG_FIELD_PREP(__mask, __val) \
166 ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
167 BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
168 BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \
169 BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) +
    [all...]

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