| /src/sys/arch/arm/include/ |
| fenv.h | 48 #define __FENV_SET_FLAGS(__envp, __val) \
49 *(__envp) = __SHIFTIN((__val), VFP_FPSCR_CSUM)
50 #define __FENV_SET_MASK(__envp, __val) \
51 *(__envp) = __SHIFTIN((__val), VFP_FPSCR_ESUM)
52 #define __FENV_SET_ROUND(__envp, __val) \
53 *(__envp) = __SHIFTIN((__val), VFP_FPSCR_RMODE)
|
| lock.h | 83 __arm_store_exclusive(__cpu_simple_lock_t *__alp, unsigned int __val)
88 : "=&r"(__rv) : "r"(__val), "r"(__alp) : "cc", "memory");
91 : "=&r"(__rv) : "r"(__val), "r"(__alp) : "cc", "memory");
97 __swp(unsigned char __val, __cpu_simple_lock_t *__ptr)
101 : "=&r" (__val32) : "r" (__val), "r" (__ptr) : "memory");
114 __swp(int __val, __cpu_simple_lock_t *__ptr)
119 "1:\t" "swp %[__rv], %[__val], [%[__ptr]]"
123 "\n\t" "strex %[__tmp],%[__val],[%[__ptr]]"
129 : [__val] "r" (__val), [__ptr] "r" (__ptr) : "cc", "memory")
[all...] |
| armreg.h | 739 static inline void armreg_##name##_write(uint32_t __val) \
741 __asm __volatile("mcr " __insnstring :: "r"(__val)); \
754 static inline void armreg_##name##_write(uint32_t __val) \
757 __asm __volatile(__insnstring :: "r"(__val)); \
769 static inline void armreg_##name##_write(uint64_t __val) \
771 __asm __volatile("mcrr " __insnstring :: "r"(__val)); \
|
| /src/sys/arch/acorn32/include/ |
| lock.h | 46 __swp(int __val, volatile unsigned char *__ptr)
50 : "=r" (__val) : "r" (__val), "r" (__ptr) : "memory");
51 return __val;
|
| /src/include/ |
| fenv.h | 68 #define __FENV_SET_FLAGS(__envp, __val) \
69 (__envp)->__flags = (__val)
70 #define __FENV_SET_MASK(__envp, __val) \
71 (__envp)->__mask = (__val)
72 #define __FENV_SET_ROUND(__envp, __val) \
73 (__envp)->__round = (__val)
|
| math.h | 26 float __val; member in union:__float_u
31 double __val; member in union:__double_u
36 long double __val; member in union:__long_double_u
87 #define HUGE_VAL __infinity.__val
101 #define HUGE_VALF __infinityf.__val
104 #define HUGE_VALL __infinityl.__val
122 #define NAN __nanf.__val
|
| /src/sys/arch/mips/rmi/ |
| rmixl_fmnvar.h | 74 uint64_t __val; \
82 : "=r"(__val) : "n"(regnum), "n"(sel)); \
83 rv = __val; \
88 uint64_t __val = val; \
96 :: "r"(__val), "n"(regnum), "n"(sel)); \
101 uint32_t __val; \
108 : "=r"(__val) : "n"(regnum), "n"(sel)); \
109 rv = __val; \
114 uint32_t __val = val; \
121 :: "r"(__val), "n"(regnum), "n"(sel));
[all...] |
| /src/sys/arch/hppa/include/ |
| lock.h | 66 int __val; local in function:__ldcw
69 : "=r" (__val) : "r" (__ptr)
72 return __val;
|
| /src/sys/arch/vax/include/ |
| mtpr.h | 177 register_t __val; local in function:mfpr
180 : "=g" (__val)
182 return __val;
|
| /src/sys/arch/aarch64/include/ |
| cpufunc.h | 228 aarch64_strip_pac(uint64_t __val)
230 if (__val & AARCH64_ADDRTOP_TAG)
231 return __val | AARCH64_ADDRESS_TAGPAC_MASK;
232 return __val & ~AARCH64_ADDRESS_TAGPAC_MASK;
|
| armreg.h | 65 reg_##regname##_write(uint64_t __val) \
69 "msr " #regdesc ", %0" :: "r"(__val) : "memory" \
78 reg_##regname##_write(const uint64_t __val) \
81 "msr " #regdesc ", %0" :: "n"(__val) : "memory" \
100 reg_##regname##_write(uint64_t __val) \
103 "at " #regdesc ", %0" :: "r"(__val) : "memory" \
|
| /src/sys/external/bsd/drm2/dist/drm/i915/gt/ |
| intel_engine.h | 89 u32 __val; \
91 __val = intel_uncore_read((engine__)->uncore, \
93 __val &= ~(clear__); \
94 __val |= (set__); \
96 __val); \
|
| /src/sys/external/bsd/drm2/dist/include/uapi/drm/ |
| drm_fourcc.h | 684 #define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \
685 fourcc_mod_code(ARM, ((__u64)(__type) << 52) | ((__val) & 0x000fffffffffffffULL))
|
| /src/sys/arch/riscv/include/ |
| sysreg.h | 121 csr_##regname##_write(uintptr_t __val) \
123 asm volatile("csrw " #regname ", %0" :: "r"(__val) : "memory"); \
|
| /src/sys/arch/mips/mips/ |
| db_interface.c | 344 uint32_t __val; \
351 : "=r"(__val) : "n"(num), "n"(sel)); \
353 FLDWIDTH - (int) strlen(name), "", __val); \
359 uint64_t __val; \
368 : "=r"(__val) : "n"(num), "n"(sel)); \
370 FLDWIDTH - (int) strlen(name), "", __val); \
|
| /src/sys/dev/ic/ |
| rtwphy.c | 62 #define GCT_WRITE(__gr, __addr, __val, __label) \
65 (__addr), (__val)) == -1) \
|
| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| i915_reg.h | 158 * @__val: value to put in the field
163 * @return: @__val masked and shifted into the field defined by @__mask.
165 #define REG_FIELD_PREP(__mask, __val) \
166 ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
170 BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
175 * @__val: value to extract the bitfield value from
180 * @return: Masked and shifted value of the field defined by @__mask in @__val.
182 #define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val))
[all...] |
