| /src/sys/arch/arm/nxp/ |
| imx6_ccmvar.h | 195 #define CLK_PLL(_name, _parent, _type, _reg, _mask, _powerdown, _ref) { \
203 .mask = (CCM_ANALOG_##_reg##_##_mask), \
210 #define CLK_DIV(_name, _parent, _reg, _mask) { \
219 .mask = (CCM_##_reg##_##_mask), \
224 #define CLK_DIV_BUSY(_name, _parent, _reg, _mask, _busy_reg, _busy_mask) { \
233 .mask = (CCM_##_reg##_##_mask), \
240 #define CLK_DIV_TABLE(_name, _parent, _reg, _mask, _tbl) { \
249 .mask = (CCM_ANALOG_##_reg##_##_mask), \
255 #define CLK_MUX(_name, _parents, _base, _reg, _mask) { \
263 .mask = (_base##_##_reg##_##_mask), \
[all...] |
| imx_ccm.h | 87 #define IMX_GATE(_id, _name, _pname, _reg, _mask) \
88 IMX_GATE_INDEX(_id, 0, _name, _pname, _reg, _mask)
89 #define IMX_GATE_INDEX(_id, _regidx, _name, _pname, _reg, _mask) \
98 .u.gate.mask = (_mask), \
268 #define IMX_DIV(_id, _name, _parent, _reg, _mask, _flags) \
269 IMX_DIV_INDEX(_id, 0, _name, _parent, _reg, _mask, _flags)
270 #define IMX_DIV_INDEX(_id, _regidx, _name, _parent, _reg, _mask, _flags) \
279 .u.div.mask = (_mask), \
|
| imx7d_ccm.c | 101 #define ANATOP_MUX(_id, _name, _parents, _reg, _mask) \
102 IMX_MUX_INDEX(_id, REGIDX_ANATOP, _name, _parents, _reg, _mask)
103 #define ANATOP_GATE(_id, _name, _parent, _reg, _mask) \
104 IMX_GATE_INDEX(_id, REGIDX_ANATOP, _name, _parent, _reg, _mask)
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/ |
| generic_regs.h | 35 .type ## _mask = DC_GPIO_GENERIC_ ## type ## __DC_GPIO_GENERIC ## id ## _ ## type ## _MASK,\
|
| ddc_regs.h | 38 .type ## _mask = DC_GPIO_DDC ## id ## _ ## type ## __DC_GPIO_DDC ## id ## cd ## _ ## type ## _MASK,\
61 .type ## _mask = DC_GPIO_DDCVGA_ ## type ## __DC_GPIO_DDCVGA ## cd ## _ ## type ## _MASK,\
78 .type ## _mask = DC_GPIO_I2CPAD_ ## type ## __DC_GPIO_ ## cd ## _ ## type ## _MASK,\
|
| hpd_regs.h | 43 .type ## _mask = DC_GPIO_HPD_ ## type ## __DC_GPIO_HPD ## id ## _ ## type ## _MASK,\
|
| amdgpu_hw_gpio.c | 40 gpio->regs->field_name ## _shift, gpio->regs->field_name ## _mask
|
| /src/sys/external/mit/xen-include-public/dist/xen/include/public/io/ |
| ring.h | 384 static inline RING_IDX name##_mask(RING_IDX idx, RING_IDX ring_size) \
393 return buf + name##_mask(idx, ring_size); \
411 *masked_cons = name##_mask(*masked_cons + size, ring_size); \
429 *masked_prod = name##_mask(*masked_prod + size, ring_size); \
441 prod = name##_mask(prod, ring_size); \
442 cons = name##_mask(cons, ring_size); \
|
| /src/sys/arch/powerpc/marvell/ |
| pic_discovery.c | 64 } _mask; member in struct:discovery_pic_ops
65 #define enable_mask _mask.mask64
66 #define enable_mask_high _mask.mask32[1]
67 #define enable_mask_low _mask.mask32[0]
|
| /src/sys/arch/arm/ti/ |
| ti_prcm.h | 146 #define TI_PRCM_HWMOD_MASK(_name, _reg, _mask, _parent, _enable, _flags) \
150 .u.hwmod.mask = (_mask), \
|
| /src/sys/arch/arm/rockchip/ |
| rk_cru.h | 391 #define RK_MUX_FLAGS(_id, _name, _parents, _reg, _mask, _flags) \
400 .u.mux.mask = (_mask), \
405 #define RK_MUX(_id, _name, _parents, _reg, _mask) \
406 RK_MUX_FLAGS(_id, _name, _parents, _reg, _mask, 0)
407 #define RK_MUXGRF(_id, _name, _parents, _reg, _mask) \
408 RK_MUX_FLAGS(_id, _name, _parents, _reg, _mask, RK_MUX_GRF)
|
| /src/sys/arch/arm/amlogic/ |
| meson_clk.h | 237 #define MESON_CLK_PLL_REG(_reg, _mask) \
238 { .reg = (_reg), .mask = (_mask) }
|
| /src/sys/external/isc/atheros_hal/dist/ |
| ah_internal.h | 339 #define ath_hal_setInterrupts(_ah, _mask) \
340 (_ah)->ah_setInterrupts(_ah, _mask)
|
| /src/sys/arch/arm/sunxi/ |
| sunxi_ccu.h | 326 #define SUNXI_CCU_PHASE(_id, _name, _parent, _reg, _mask) \
332 .u.phase.mask = (_mask), \
|
| /src/sys/arch/riscv/starfive/ |
| jh7110_pinctrl.c | 224 #define JH7110_FS(_reg, _mask, _max) \
228 .jfs_mask = (_mask), \
|
| /src/sys/dev/ic/ |
| athvar.h | 348 #define ath_hal_intrset(_ah, _mask) \
349 ((*(_ah)->ah_setInterrupts)((_ah), (_mask)))
|
| /src/sys/dev/pci/ |
| cxdtv.c | 1090 #define cxdtv_write_field(_mask, _shift, _value) \
1091 (((_value) & (_mask)) << (_shift))
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/fb/ |
| nouveau_nvkm_subdev_fb_ramgk104.c | 235 u32 _mask, u32 _data, u32 _copy)
241 u32 mask = _mask | _copy;
242 u32 data = (_data & _mask) | (reg->data & _copy);
|
| /src/sys/dev/i2c/ |
| axppmic.c | 409 #define AXPPMIC_IRQ(_reg, _mask) \
410 { .reg = (_reg), .mask = (_mask) }
|
| /src/sys/external/isc/atheros_hal/dist/ar5212/ |
| ar5212_reset.c | 1481 #define AR_PHY_BIS(_ah, _reg, _mask, _val) \
1483 (OS_REG_READ(_ah, AR_PHY(_reg)) & _mask) | (_val));
|
| /src/sys/net/lagg/ |
| if_lagg_lacp.c | 235 #define LACP_STATE_EQ(_s1, _s2, _mask) (!ISSET((_s1) ^ (_s2), (_mask)))
|
