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    Searched refs:_reg_read_1 (Results 1 - 23 of 23) sorted by relevancy

  /src/sys/arch/evbsh3/t_sh7706lan/
t_sh7706lanvar.h 34 #define IS_SH7706LSR (_reg_read_1(T_SH7706LSR_ID) == 0xab)
ssumci.c 108 _r = _reg_read_1((reg)); \
126 _r = _reg_read_1((reg)); \
182 while (_reg_read_1(SSUMCI_SPISR) == 0x00)
191 return _reg_read_1(SSUMCI_SPIBR);
287 reg = _reg_read_1(SH7709_SCPDR);
537 if ((_reg_read_1(SSUMCI_SPIDR) & 0x0f) != 5) {
545 c = _reg_read_1(SSUMCI_SPIDR);
scimci.c 106 _r = _reg_read_1((reg)); \
124 _r = _reg_read_1((reg)); \
350 reg = _reg_read_1(SH7709_PGDR);
  /src/sys/arch/hpcsh/dev/
psh3pwr.c 76 return _reg_read_1(SH7709_SCPDR) & PSH3PWR_PLUG_OUT;
146 phdr = _reg_read_1(SH7709_PHDR);
171 irr0 = _reg_read_1(SH7709_IRR0);
178 scpdr = _reg_read_1(SH7709_SCPDR);
191 irr0 = _reg_read_1(SH7709_IRR0);
197 scpdr = _reg_read_1(SH7709_SCPDR);
213 phdr = _reg_read_1(SH7709_PHDR);
218 phdr = _reg_read_1(SH7709_PHDR);
psh3lcd.c 138 bcr0 = _reg_read_1(PSH3LCD_BRIGHTNESS_REG0);
139 bcr1 = _reg_read_1(PSH3LCD_BRIGHTNESS_REG1);
140 bcr2 = _reg_read_1(PSH3LCD_BRIGHTNESS_REG2);
158 bcr1 = _reg_read_1(PSH3LCD_BRIGHTNESS_REG1);
159 bcr2 = _reg_read_1(PSH3LCD_BRIGHTNESS_REG2);
203 pddr = _reg_read_1(SH7709_PDDR);
235 bcr0 = _reg_read_1(PSH3LCD_BRIGHTNESS_REG0);
256 bcr0 = _reg_read_1(PSH3LCD_BRIGHTNESS_REG0);
257 (void)_reg_read_1(PSH3LCD_BRIGHTNESS_REG1);
258 (void)_reg_read_1(PSH3LCD_BRIGHTNESS_REG2)
    [all...]
pfckbd.c 320 data = _reg_read_1(SH7709_PFDR)
321 | (_reg_read_1(SH7709_PCDR) << 8);
336 data = _reg_read_1(SH7709_PGDR) | (_reg_read_1(SH7709_PHDR) << 8);
413 cd = _reg_read_1(SH7709_PCDR) & ~PFCKBD_HITACHI_PCDR_SCN_MASK;
414 dd = _reg_read_1(SH7709_PDDR) & ~PFCKBD_HITACHI_PDDR_SCN_MASK;
415 ed = _reg_read_1(SH7709_PEDR) & ~PFCKBD_HITACHI_PEDR_SCN_MASK;
425 (_reg_read_1(SH7709_PCDR) & PFCKBD_HITACHI_PCDR_SNS_MASK)
426 | (_reg_read_1(SH7709_PFDR) & PFCKBD_HITACHI_PFDR_SNS_MASK);
463 cd = _reg_read_1(SH7709_PCDR) & ~PFCKBD_HITACHI_PCDR_SCN_MASK
    [all...]
psh3tp.c 283 irr0 = _reg_read_1(SH7709_IRR0);
309 phdr = _reg_read_1(SH7709_PHDR);
357 phdr = _reg_read_1(SH7709_PHDR);
394 irr0 = _reg_read_1(SH7709_IRR0);
422 phdr = _reg_read_1(SH7709_PHDR);
465 scpdr = _reg_read_1(SH7709_SCPDR);
474 scpdr = _reg_read_1(SH7709_SCPDR);
483 scpdr = _reg_read_1(SH7709_SCPDR);
j6x0tp.c 374 irr0 = _reg_read_1(SH7709_IRR0);
401 phdr = _reg_read_1(SH7709_PHDR);
451 phdr = _reg_read_1(SH7709_PHDR);
504 irr0 = _reg_read_1(SH7709_IRR0);
532 phdr = _reg_read_1(SH7709_PHDR);
568 phdr = _reg_read_1(SH7709_PHDR);
612 scpdr = _reg_read_1(SH7709_SCPDR);
621 scpdr = _reg_read_1(SH7709_SCPDR);
630 scpdr = _reg_read_1(SH7709_SCPDR);
j6x0pwr.c 63 return _reg_read_1(SH7709_PGDR) & PGDR_MAIN_BATTERY_OUT;
70 return _reg_read_1(SH7709_PJDR) & PJDR_AC_POWER_OUT;
78 return _reg_read_1(SH7709_PLDR) & PLDR_BATTERY_CHARGED;
220 pgdr = _reg_read_1(SH7709_PGDR);
248 irr0 = _reg_read_1(SH7709_IRR0);
  /src/sys/arch/evbsh3/ap_ms104_sh4/
ap_ms104_sh4_intr.c 162 reg = _reg_read_1(EXTINTR_MASK4);
168 reg = _reg_read_1(EXTINTR_MASK3);
174 reg = _reg_read_1(EXTINTR_MASK2);
180 reg = _reg_read_1(EXTINTR_MASK1);
237 reg = _reg_read_1(EXTINTR_MASK4);
243 reg = _reg_read_1(EXTINTR_MASK3);
249 reg = _reg_read_1(EXTINTR_MASK2);
255 reg = _reg_read_1(EXTINTR_MASK1);
shpcmcia.c 818 while (_reg_read_1(EXTINTR_STAT1) & MASK1_INT12)
  /src/sys/arch/hpc/stand/hpcboot/sh3/dev/
sh3_dev.cpp 116 DPRINTF((TEXT("IRR0 0x%08x\n"), _reg_read_1(SH3_IRR0)));
117 DPRINTF((TEXT("IRR1 0x%08x\n"), _reg_read_1(SH3_IRR1)));
118 DPRINTF((TEXT("IRR2 0x%08x\n"), _reg_read_1(SH3_IRR2)));
212 bitdisp(_reg_read_1(SH3_P##x##DR))
226 bitdisp(_reg_read_1(SH3_SCPDR));
237 r8 = _reg_read_1(SH3_TOCR);
241 r8 = _reg_read_1(SH3_TSTR);
417 r8 = _reg_read_1(HD64461_PCC0ISR_REG8);
432 r8 = _reg_read_1(HD64461_PCC0GCR_REG8);
447 r8 = _reg_read_1(HD64461_PCC0CSCR_REG8)
    [all...]
sh_dev.h 77 return (uint32_t)_reg_read_1(va);
sh.h 224 while ((_reg_read_1(SH3_SCSSR) & SCSSR_TDRE) == 0)
231 _reg_read_1(SH3_SCSSR) & ~SCSSR_TDRE); \
346 _reg_read_1(SH3_SCSSR2) & ~(SCSSR2_TDFE | SCSSR2_TEND)); \
  /src/sys/arch/playstation2/ee/
eevar.h 41 #define _reg_read_1(a) __read_1(a) macro
  /src/sys/arch/sh3/dev/
rtc.c 98 r = _reg_read_1(SH_(RCR2));
162 uint8_t r = _reg_read_1(SH_(RCR1));
168 year = _reg_read_1(SH3_RYRCNT);
175 dt->dt_ ## x = bcdtobin(_reg_read_1(SH_(R ## y ## CNT)))
184 } while ((_reg_read_1(SH_(RCR1)) & SH_RCR1_CF) && --retry > 0);
224 r = _reg_read_1(SH_(RCR2));
  /src/sys/arch/sh3/include/
devreg.h 38 #define _reg_read_1(a) (*(volatile uint8_t *)((vaddr_t)(a))) macro
  /src/sys/arch/hpc/stand/hpcboot/
hpcboot.h 124 #define _reg_read_1(a) (*(volatile uint8_t *)(a)) macro
  /src/sys/arch/landisk/dev/
pwrsw_obio.c 121 status = (int8_t)_reg_read_1(LANDISK_BTNSTAT);
btn_obio.c 165 status = (int8_t)_reg_read_1(LANDISK_BTNSTAT);
  /src/sys/arch/playstation2/dev/
if_smap.c 294 if (_reg_read_1(SMAP_RXFIFO_FRAME_REG8) > 0)
303 sc->tx_desc_cnt > _reg_read_1(SMAP_TXFIFO_FRAME_REG8))
631 while ((_reg_read_1(a) & SMAP_FIFO_RESET) && --retry > 0)
716 _reg_read_1(SMAP_TXFIFO_FRAME_REG8),
717 _reg_read_1(SMAP_RXFIFO_FRAME_REG8), __sc->tx_desc_cnt,
spd.c 266 ret = (_reg_read_1(SPD_IO_DATA_REG8) >> 4) & 0x1;
  /src/sys/arch/landisk/landisk/
intr.c 96 inten = _reg_read_1(LANDISK_INTEN);

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