| /src/sys/arch/evbsh3/ap_ms104_sh4/ |
| ap_ms104_sh4_intr.c | 78 _reg_write_1(EXTINTR_MASK1, 0);
79 _reg_write_1(EXTINTR_MASK2, 0);
80 _reg_write_1(EXTINTR_MASK3, 0);
81 _reg_write_1(EXTINTR_MASK4, 0);
164 _reg_write_1(EXTINTR_MASK4, reg);
170 _reg_write_1(EXTINTR_MASK3, reg);
176 _reg_write_1(EXTINTR_MASK2, reg);
182 _reg_write_1(EXTINTR_MASK1, reg);
239 _reg_write_1(EXTINTR_MASK4, reg);
245 _reg_write_1(EXTINTR_MASK3, reg)
[all...] |
| /src/sys/arch/hpcsh/dev/ |
| psh3pwr.c | 147 _reg_write_1(SH7709_PHDR, phdr | PSH3_GREEN_LED_ON);
175 _reg_write_1(SH7709_IRR0, irr0 & ~IRR0_IRQ0);
179 _reg_write_1(SH7709_SCPDR, scpdr | PSH3PWR_PLUG_OUT);
194 _reg_write_1(SH7709_IRR0, irr0 & ~IRR0_IRQ1);
198 _reg_write_1(SH7709_SCPDR, scpdr & ~PSH3PWR_PLUG_OUT);
214 _reg_write_1(SH7709_PHDR, phdr & ~PSH3_GREEN_LED_ON);
219 _reg_write_1(SH7709_PHDR, phdr | PSH3_GREEN_LED_ON);
|
| psh3lcd.c | 174 _reg_write_1(PSH3LCD_BRIGHTNESS_REG1, psh3lcd_xx0_bcd[index].reg1);
175 _reg_write_1(PSH3LCD_BRIGHTNESS_REG2, psh3lcd_xx0_bcd[index].reg2);
182 _reg_write_1(PSH3LCD_BRIGHTNESS_REG0, psh3lcd_x0_bcd[index].reg0);
183 _reg_write_1(PSH3LCD_BRIGHTNESS_REG1, psh3lcd_x0_bcd[index].reg1);
184 _reg_write_1(PSH3LCD_BRIGHTNESS_REG2, psh3lcd_x0_bcd[index].reg2);
208 _reg_write_1(SH7709_PDDR, pddr);
|
| pfckbd.c | 315 _reg_write_1(SH7709_PDDR, scan[column].d);
316 _reg_write_1(SH7709_PEDR, scan[column].e);
327 _reg_write_1(SH7709_PDDR, 0xff);
328 _reg_write_1(SH7709_PEDR, 0xff);
418 _reg_write_1(SH7709_PCDR, cd | scan[i].c);
419 _reg_write_1(SH7709_PDDR, dd | scan[i].d);
420 _reg_write_1(SH7709_PEDR, ed | scan[i].e);
468 _reg_write_1(SH7709_PCDR, cd | poll.c);
469 _reg_write_1(SH7709_PDDR, dd | poll.d);
470 _reg_write_1(SH7709_PEDR, ed | poll.e)
[all...] |
| j6x0pwr.c | 188 _reg_write_1(SH7709_PKDR, 0); /* Green LED on */
250 _reg_write_1(SH7709_IRR0, irr0 & ~IRR0_IRQ0);
271 _reg_write_1(SH7709_PKDR, 0xff); /* Green LED off */
275 _reg_write_1(SH7709_PKDR, 0); /* Green LED on */
|
| psh3tp.c | 340 _reg_write_1(SH7709_IRR0, irr0 & ~IRR0_IRQ2);
396 _reg_write_1(SH7709_IRR0, irr0 & ~IRR0_IRQ2);
468 _reg_write_1(SH7709_SCPDR, scpdr);
477 _reg_write_1(SH7709_SCPDR, scpdr);
486 _reg_write_1(SH7709_SCPDR, scpdr);
|
| j6x0tp.c | 431 _reg_write_1(SH7709_IRR0, irr0 & ~IRR0_IRQ3);
506 _reg_write_1(SH7709_IRR0, irr0 & ~IRR0_IRQ3);
615 _reg_write_1(SH7709_SCPDR, scpdr);
624 _reg_write_1(SH7709_SCPDR, scpdr);
633 _reg_write_1(SH7709_SCPDR, scpdr);
|
| /src/sys/arch/playstation2/dev/ |
| spd.c | 193 _reg_write_1(SPD_IO_DIR_REG8, SPD_IO_CLK | SPD_IO_CS | SPD_IO_IN);
197 _reg_write_1(SPD_IO_DATA_REG8, r);
201 _reg_write_1(SPD_IO_DATA_REG8, r);
222 _reg_write_1(SPD_IO_DATA_REG8, r);
239 _reg_write_1(SPD_IO_DATA_REG8, r);
243 _reg_write_1(SPD_IO_DATA_REG8, r);
247 _reg_write_1(SPD_IO_DATA_REG8, r);
260 _reg_write_1(SPD_IO_DATA_REG8, r);
264 _reg_write_1(SPD_IO_DATA_REG8, r);
269 _reg_write_1(SPD_IO_DATA_REG8, r)
[all...] |
| if_smap.c | 185 _reg_write_1(SMAP_DESC_MODE_REG8, 0);
384 _reg_write_1(SMAP_RXFIFO_FRAME_DEC_REG8, 1);
525 _reg_write_1(SMAP_TXFIFO_FRAME_INC_REG8, 1);
629 _reg_write_1(a, SMAP_FIFO_RESET);
|
| /src/sys/arch/mmeye/stand/boot/ |
| clock.c | 40 _reg_write_1(SH_(TOCR), TOCR_TCOE);
|
| /src/sys/arch/sh3/dev/ |
| rtc.c | 115 _reg_write_1(SH_(RCR1), 0);
118 _reg_write_1(SH_(RCR2), SH_RCR2_ENABLE | SH_RCR2_START);
165 _reg_write_1(SH_(RCR1), r);
227 _reg_write_1(SH_(RCR2), (r & ~SH_RCR2_START) | SH_RCR2_RESET);
231 _reg_write_1(SH3_RYRCNT, year);
236 _reg_write_1(SH_(R ## x ## CNT), bintobcd(dt->dt_ ## y))
248 _reg_write_1(SH_(RCR2), r);
|
| /src/sys/arch/playstation2/ee/ |
| eevar.h | 46 #define _reg_write_1(a, v) __write_1(a, v) macro
|
| /src/sys/arch/landisk/dev/ |
| rs5c313_landisk.c | 118 _reg_write_1(LANDISK_PWRMNG, PWRMNG_RTC_CE);
120 _reg_write_1(LANDISK_PWRMNG, 0);
|
| pwrsw_obio.c | 137 _reg_write_1(LANDISK_PWRSW_INTCLR, 1);
|
| /src/sys/arch/sh3/include/ |
| devreg.h | 41 #define _reg_write_1(a, v) \ macro
|
| /src/sys/arch/landisk/stand/boot/ |
| getsecs.c | 71 _reg_write_1(0xb0000003, (1 << 1));
73 _reg_write_1(0xb0000003, (0 << 1));
|
| /src/sys/arch/hpc/stand/hpcboot/sh3/dev/ |
| sh.h | 229 _reg_write_1(SH3_SCTDR, c); \
230 _reg_write_1(SH3_SCSSR, \
343 _reg_write_1(SH3_SCFTDR2, c); \
345 _reg_write_1(SH3_SCSSR2, \
|
| /src/sys/arch/landisk/landisk/ |
| intr.c | 97 _reg_write_1(LANDISK_INTEN, inten & ~bit);
104 _reg_write_1(LANDISK_INTEN, inten);
131 _reg_write_1(LANDISK_INTEN, INTEN_ALL_MASK);
|
| machdep.c | 337 _reg_write_1(LANDISK_PWRMNG, PWRMNG_POWEROFF);
449 _reg_write_1(BSC_SDMR2_VAL, 0);
453 _reg_write_1(BSC_SDMR3_VAL, 0);
|
| /src/sys/arch/sh3/sh3/ |
| clock.c | 124 _reg_write_1(SH_(RCR1), 0);
127 _reg_write_1(SH_(TSTR), 0);
183 _reg_write_1(SH_(TSTR), 0);
|
| sh3_machdep.c | 215 _reg_write_1(SH4_BAMRA, SH4_UBC_MASK_NONE | SH4_UBC_MASK_ASID);
|
| /src/sys/arch/evbsh3/evbsh3/ |
| machdep.c | 424 _reg_write_1(BSC_SDMR2_VAL, 0);
429 _reg_write_1(BSC_SDMR3_VAL, 0);
432 _reg_write_1(BSC_SDMR3_VAL, 0);
|
| /src/sys/arch/hpc/stand/hpcboot/ |
| hpcboot.h | 127 #define _reg_write_1(a, v) (*(volatile uint8_t *)(a) = (v)) macro
|
| /src/sys/arch/evbsh3/t_sh7706lan/ |
| ssumci.c | 111 _reg_write_1((reg), _r); \
128 _reg_write_1((reg), _r); \
198 _reg_write_1(SSUMCI_SPIDR, v);
|
| scimci.c | 109 _reg_write_1((reg), _r); \
126 _reg_write_1((reg), _r); \
|
