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    Searched refs:_val (Results 1 - 17 of 17) sorted by relevancy

  /src/sys/dev/fdt/
syscon.h 50 #define syscon_write_4(_syscon, _reg, _val) \
51 (_syscon)->write_4((_syscon)->priv, (_reg), (_val))
  /src/sys/arch/alpha/tlsb/
tlsbreg.h 74 #define TLSB_PUT_NODEREG(_node, _reg, _val) \
75 *(volatile uint32_t *)(TLSB_NODE_REG_ADDR((_node), (_reg))) = (_val)
88 #define TLSB_PUT_BCASTREG(_reg, _val) \
89 *(volatile uint32_t *)(TLSB_BCAST_REG_ADDR + (_reg)) = (_val)
198 #define TLDEV_DTYPE(_val) ((_val) & TLDEV_DTYPE_MASK)
199 # define TLDEV_ISCPU(_val) (TLDEV_DTYPE(_val) & 0x8000)
200 # define TLDEV_ISMEM(_val) (TLDEV_DTYPE(_val) & 0x4000
    [all...]
  /src/sys/arch/arm/at91/
at91rm9200reg.h 199 #define PIOA_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91RM9200_PIOA_BASE + (_reg))) = (_val);} while (0)
201 #define PIOB_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91RM9200_PIOB_BASE + (_reg))) = (_val);} while (0)
203 #define PIOC_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91RM9200_PIOC_BASE + (_reg))) = (_val);} while (0)
205 #define PIOD_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91RM9200_PIOD_BASE + (_reg))) = (_val);} while (0)
at91sam9260reg.h 214 #define PIOA_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91SAM9260_PIOA_BASE + (_reg))) = (_val);} while (0)
216 #define PIOB_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91SAM9260_PIOB_BASE + (_reg))) = (_val);} while (0)
218 #define PIOC_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91SAM9260_PIOC_BASE + (_reg))) = (_val);} while (0)
at91sam9261reg.h 212 #define PIOA_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91SAM9261_PIOA_BASE + (_reg))) = (_val);} while (0)
214 #define PIOB_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91SAM9261_PIOB_BASE + (_reg))) = (_val);} while (0)
216 #define PIOC_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91SAM9261_PIOC_BASE + (_reg))) = (_val);} while (0)
at91pio.c 70 #define PIO_WRITE(_sc, _reg, _val) bus_space_write_4((_sc)->sc_iot, (_sc)->sc_ioh, (_reg), (_val))
  /src/sys/external/isc/atheros_hal/ic/
ah_osdep.h 93 #define OS_REG_WRITE(_ah, _reg, _val) ath_hal_reg_write(_ah, _reg, _val)
112 #define OS_REG_WRITE(_ah, _reg, _val) do { \
115 (_reg), (_val)); \
118 (_reg), (_val)); \
125 #define OS_REG_WRITE(_ah, _reg, _val) \
126 bus_space_write_4((_ah)->ah_st, (_ah)->ah_sh, (_reg), (_val))
  /src/sys/external/isc/atheros_hal/dist/ar5210/
ar5210.h 30 #define AR5210_TXD_CTRL_A_HDR_LEN(_val) (((_val) ) & 0x0003f)
31 #define AR5210_TXD_CTRL_A_TX_RATE(_val) (((_val) << 6) & 0x003c0)
33 #define AR5210_TXD_CTRL_A_CLEAR_DEST_MASK(_val) (((_val) << 12) & 0x01000)
34 #define AR5210_TXD_CTRL_A_ANT_MODE(_val) (((_val) << 13) & 0x02000)
35 #define AR5210_TXD_CTRL_A_PKT_TYPE(_val) (((_val) << 14) & 0x1c000
    [all...]
  /src/sys/arch/sparc64/include/
psl.h 317 type _val; \
318 __asm(#rd " %" #reg ",%0" : "=r" (_val) : : constasm_clobbers); \
319 return _val; \
324 type _val; \
325 __asm volatile(#rd " %" #reg ",%0" : "=r" (_val)); \
326 return _val; \
329 static __inline void set##name(type _val) \
331 __asm volatile(#wr " %0,0,%" #reg : : "r" (_val) : "memory"); \
357 static __inline void set##name(uint64_t _val) \
359 uint32_t _hi = _val >> 32, _lo = _val;
    [all...]
  /src/sys/external/isc/atheros_hal/dist/ar5312/
ar5312reg.h 31 #define REG_WRITE(_reg,_val) *((volatile uint32_t *)(_reg)) = (_val);
  /src/sys/external/isc/atheros_hal/dist/
ah_internal.h 325 #define ath_hal_gpioSet(_ah, _gpio, _val) \
326 AH_PRIVATE(_ah)->ah_gpioGet(_ah, _gpio, _val)
347 #define ath_hal_eepromGet(_ah, _param, _val) \
348 AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val)
349 #define ath_hal_eepromSet(_ah, _param, _val) \
350 AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val)
  /src/sys/arch/sun68k/sun68k/
autoconf.c 289 str2hex(const char *p, int *_val)
305 *_val = val;
  /src/usr.bin/rump_dhcpclient/
dhcp.c 500 #define PUTADDR(_type, _val) \
504 memcpy(p, &_val.s_addr, 4); \
  /src/sys/dev/ic/
advlib.c 1812 u_int16_t _val; local
1817 _val = AscReadLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_STATUS);
1818 scsiq->q_status = LO_BYTE(_val);
1819 scsiq->q_no = HI_BYTE(_val);
1820 _val = AscReadLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_CNTL);
1821 scsiq->cntl = LO_BYTE(_val);
1822 sg_queue_cnt = HI_BYTE(_val);
1823 _val = AscReadLramWord(iot, ioh, q_addr + ASC_SCSIQ_B_SENSE_LEN);
1824 scsiq->sense_len = LO_BYTE(_val);
1825 scsiq->extra_bytes = HI_BYTE(_val);
    [all...]
  /src/sys/net/lagg/
if_lagg_lacp.c 223 #define LACP_TIMER_ARM(_lacpp, _timer, _val) \
224 (_lacpp)->lp_timer[(_timer)] = (_val)
229 #define LACP_PTIMER_ARM(_sc, _timer, _val) \
230 (_sc)->lsc_timer[(_timer)] = (_val)
  /src/sys/dev/pci/
if_iwmreg.h 295 #define IWM_CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0)
296 #define IWM_CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2)
  /src/sys/external/isc/atheros_hal/dist/ar5212/
ar5212_reset.c 1481 #define AR_PHY_BIS(_ah, _reg, _mask, _val) \
1483 (OS_REG_READ(_ah, AR_PHY(_reg)) & _mask) | (_val));

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