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Searched
refs:a08
(Results
1 - 7
of
7
) sorted by relevancy
/src/tests/usr.bin/xlint/lint1/
decl_direct_abstract.c
141
}
a08
;
typedef in typeref:struct:__anon9a30da6a0308
153
/* expect+2: error: cannot take size/alignment of function type 'function() returning struct typedef
a08
' [144] */
155
int unspecified_args_return_08[-1000 - (int)sizeof(
a08
())];
166
/* expect+2: error: cannot take size/alignment of function type 'function(void) returning struct typedef
a08
' [144] */
168
int prototype_void_return_08[-1000 - (int)sizeof(
a08
(void))];
179
/* expect+2: error: cannot take size/alignment of function type 'function(struct typedef
a08
) returning struct typedef a32' [144] */
181
int prototype_unnamed_08_return_32[-1000 - (int)sizeof(a32(
a08
))];
192
/* expect+2: error: cannot take size/alignment of function type 'function(struct typedef a32) returning struct typedef
a08
' [144] */
194
int prototype_unnamed_32_return_08[-1000 - (int)sizeof(
a08
(a32))];
202
/* expect+2: error: cannot take size/alignment of function type 'function(struct typedef
a08
) returning struct typedef a32' [144] *
[
all
...]
/src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/nvidia/
Makefile
8
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2894-0050-
a08
.dtb
/src/sys/external/gpl2/dts/dist/arch/mips/boot/dts/loongson/
ls7a-pch.dtsi
120
compatible = "pci0014,7
a08
.0",
121
"pci0014,7
a08
",
131
compatible = "pci0014,7
a08
.0",
132
"pci0014,7
a08
",
142
compatible = "pci0014,7
a08
.0",
143
"pci0014,7
a08
",
loongson64-2k1000.dtsi
186
compatible = "pci0014,7
a08
.0",
187
"pci0014,7
a08
",
/src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
omap36xx-am35xx-omap3430es2plus-clocks.dtsi
112
cpefuse_fck: cpefuse_fck@
a08
{
120
ts_fck: ts_fck@
a08
{
128
usbtll_fck: usbtll_fck@
a08
{
/src/sys/arch/m68k/060sp/dist/
pfpsp.sa
814
dc.l $00000
a08
,$0a080a08,$0a080a08,$0a087fff
1622
dc.l $00000590,$20016
a08
,$44800090,$40000000
fpsp.sa
3229
dc.l $00000
a08
,$0a080a08,$0a080a08,$0a087fff
Completed in 19 milliseconds
Indexes created Wed Oct 15 16:09:53 GMT 2025