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  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/acr/
nouveau_nvkm_subdev_acr_base.c 34 nvkm_acr_hsf_find(struct nvkm_acr *acr, const char *name)
37 list_for_each_entry(hsf, &acr->hsf, head) {
45 nvkm_acr_hsf_boot(struct nvkm_acr *acr, const char *name)
47 struct nvkm_subdev *subdev = &acr->subdev;
51 hsf = nvkm_acr_hsf_find(acr, name);
60 ret = hsf->func->boot(acr, hsf);
72 nvkm_acr_unload(struct nvkm_acr *acr)
74 if (acr->done) {
75 nvkm_acr_hsf_boot(acr, "unload");
76 acr->done = false
129 struct nvkm_acr *acr = device->acr; local in function:nvkm_acr_falcon
146 struct nvkm_acr *acr = device->acr; local in function:nvkm_acr_bootstrap_falcons
174 struct nvkm_acr *acr = device->acr; local in function:nvkm_acr_managed_falcon
216 struct nvkm_acr *acr = nvkm_acr(subdev); local in function:nvkm_acr_oneinit
329 struct nvkm_acr *acr = nvkm_acr(subdev); local in function:nvkm_acr_dtor
391 struct nvkm_acr *acr; local in function:nvkm_acr_new_
    [all...]
nouveau_nvkm_subdev_acr_gm20b.c 34 #include <nvfw/acr.h>
38 gm20b_acr_wpr_alloc(struct nvkm_acr *acr, u32 wpr_size)
40 struct nvkm_subdev *subdev = &acr->subdev;
42 acr->func->wpr_check(acr, &acr->wpr_start, &acr->wpr_end);
44 if ((acr->wpr_end - acr->wpr_start) < wpr_size) {
50 wpr_size, 0, true, &acr->wpr)
    [all...]
nouveau_nvkm_subdev_acr_gp102.c 34 #include <nvfw/acr.h>
40 gp102_acr_wpr_patch(struct nvkm_acr *acr, s64 adjust)
48 nvkm_robj(acr->wpr, offset, &hdr, sizeof(hdr));
49 wpr_header_v1_dump(&acr->subdev, &hdr);
51 list_for_each_entry(lsfw, &acr->lsfw, head) {
55 nvkm_robj(acr->wpr, hdr.lsb_offset, &lsb, sizeof(lsb));
56 lsb_header_v1_dump(&acr->subdev, &lsb);
58 lsfw->func->bld_patch(acr, lsb.tail.bl_data_off, adjust);
67 gp102_acr_wpr_build_lsb(struct nvkm_acr *acr, struct nvkm_acr_lsfw *lsfw)
77 nvkm_wobj(acr->wpr, lsfw->offset.lsb, &hdr, sizeof(hdr))
    [all...]
nouveau_nvkm_subdev_acr_tu102.c 35 #include <nvfw/acr.h>
38 tu102_acr_init(struct nvkm_acr *acr)
40 int ret = nvkm_acr_hsf_boot(acr, "AHESASC");
44 return nvkm_acr_hsf_boot(acr, "ASB");
48 tu102_acr_wpr_build(struct nvkm_acr *acr, struct nvkm_acr_lsf *rtos)
55 nvkm_wo32(acr->wpr, 0x200, 0xffffffff);
58 list_for_each_entry(lsfw, &acr->lsfw, head) {
70 nvkm_wobj(acr->wpr, offset, &hdr, sizeof(hdr));
74 ret = gp102_acr_wpr_build_lsb(acr, lsfw);
79 nvkm_wobj(acr->wpr, lsfw->offset.img
    [all...]
nouveau_nvkm_subdev_acr_gm200.c 37 #include <nvfw/acr.h>
43 gm200_acr_init(struct nvkm_acr *acr)
45 return nvkm_acr_hsf_boot(acr, "load");
49 gm200_acr_wpr_check(struct nvkm_acr *acr, u64 *start, u64 *limit)
51 struct nvkm_device *device = acr->subdev.device;
61 gm200_acr_wpr_patch(struct nvkm_acr *acr, s64 adjust)
63 struct nvkm_subdev *subdev = &acr->subdev;
70 nvkm_robj(acr->wpr, offset, &hdr, sizeof(hdr));
73 list_for_each_entry(lsfw, &acr->lsfw, head) {
77 nvkm_robj(acr->wpr, hdr.lsb_offset, &lsb, sizeof(lsb))
    [all...]
nouveau_nvkm_subdev_acr_lsfw.c 45 nvkm_acr_lsfw_del_all(struct nvkm_acr *acr)
48 list_for_each_entry_safe(lsfw, lsft, &acr->lsfw, head) {
54 nvkm_acr_lsfw_get(struct nvkm_acr *acr, enum nvkm_acr_lsf_id id)
57 list_for_each_entry(lsfw, &acr->lsfw, head) {
65 nvkm_acr_lsfw_add(const struct nvkm_acr_lsf_func *func, struct nvkm_acr *acr,
70 if (!acr)
73 lsfw = nvkm_acr_lsfw_get(acr, id);
75 nvkm_error(&acr->subdev, "LSFW %d redefined\n", id);
84 list_add_tail(&lsfw->head, &acr->lsfw);
100 struct nvkm_acr *acr = subdev->device->acr local in function:nvkm_acr_lsfw_load_sig_image_desc_
193 struct nvkm_acr *acr = subdev->device->acr; local in function:nvkm_acr_lsfw_load_bl_inst_data_sig
    [all...]
nouveau_nvkm_subdev_acr_hsfw.c 46 nvkm_acr_hsfw_del_all(struct nvkm_acr *acr)
49 list_for_each_entry_safe(hsfw, hsft, &acr->hsfw, head) {
55 nvkm_acr_hsfw_load_image(struct nvkm_acr *acr, const char *name, int ver,
58 struct nvkm_subdev *subdev = &acr->subdev;
134 nvkm_acr_hsfw_load_bl(struct nvkm_acr *acr, const char *name, int ver,
137 struct nvkm_subdev *subdev = &acr->subdev;
162 nvkm_acr_hsfw_load(struct nvkm_acr *acr, const char *bl, const char *fw,
174 list_add_tail(&hsfw->head, &acr->hsfw);
176 ret = nvkm_acr_hsfw_load_bl(acr, bl, version, hsfw);
180 ret = nvkm_acr_hsfw_load_image(acr, fw, version, hsfw)
    [all...]
nouveau_nvkm_subdev_acr_gp108.c 34 gp108_acr_hsfw_bld(struct nvkm_acr *acr, struct nvkm_acr_hsf *hsf)
50 flcn_bl_dmem_desc_v2_dump(&acr->subdev, &hsdesc);
62 MODULE_FIRMWARE("nvidia/gp108/acr/unload_bl.bin");
63 MODULE_FIRMWARE("nvidia/gp108/acr/ucode_unload.bin");
65 MODULE_FIRMWARE("nvidia/gv100/acr/unload_bl.bin");
66 MODULE_FIRMWARE("nvidia/gv100/acr/ucode_unload.bin");
81 MODULE_FIRMWARE("nvidia/gp108/acr/bl.bin");
82 MODULE_FIRMWARE("nvidia/gp108/acr/ucode_load.bin");
84 MODULE_FIRMWARE("nvidia/gv100/acr/bl.bin");
85 MODULE_FIRMWARE("nvidia/gv100/acr/ucode_load.bin")
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/gr/
nouveau_nvkm_engine_gr_gp108.c 29 #include <subdev/acr.h>
34 gp108_gr_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust)
37 nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr));
40 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
41 flcn_bl_dmem_desc_v2_dump(&acr->subdev, &hdr);
45 gp108_gr_acr_bld_write(struct nvkm_acr *acr, u32 bld,
61 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
nouveau_nvkm_engine_gr_gm20b.c 31 #include <subdev/acr.h>
39 gm20b_gr_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust)
44 nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr));
51 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
53 flcn_bl_dmem_desc_dump(&acr->subdev, &hdr);
57 gm20b_gr_acr_bld_write(struct nvkm_acr *acr, u32 bld,
75 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
92 if (!device->acr) {
nouveau_nvkm_engine_gr_gm200.c 33 #include <subdev/acr.h>
45 gm200_gr_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust)
48 nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr));
51 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
52 flcn_bl_dmem_desc_v1_dump(&acr->subdev, &hdr);
56 gm200_gr_acr_bld_write(struct nvkm_acr *acr, u32 bld,
72 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
nouveau_nvkm_engine_gr_gp10b.c 31 #include <subdev/acr.h>
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/sec2/
nouveau_nvkm_engine_sec2_gp108.c 28 #include <subdev/acr.h>
priv.h 22 const struct nvkm_acr_lsf_func *acr; member in struct:nvkm_sec2_fwif
nouveau_nvkm_engine_sec2_gp102.c 30 #include <subdev/acr.h>
85 gp102_sec2_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust)
88 nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr));
92 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
93 loader_config_v1_dump(&acr->subdev, &hdr);
97 gp102_sec2_acr_bld_write(struct nvkm_acr *acr, u32 bld,
114 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
266 gp102_sec2_acr_bld_patch_1(struct nvkm_acr *acr, u32 bld, s64 adjust)
269 nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr));
272 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr))
    [all...]
nouveau_nvkm_engine_sec2_tu102.c 28 #include <subdev/acr.h>
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/pmu/
nouveau_nvkm_subdev_pmu_gm20b.c 30 #include <subdev/acr.h>
81 gm20b_pmu_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust)
86 nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr));
96 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
98 loader_config_dump(&acr->subdev, &hdr);
102 gm20b_pmu_acr_bld_write(struct nvkm_acr *acr, u32 bld,
124 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
146 nvkm_error(subdev, "ACR WPR init failure: %d\n",
151 nvkm_debug(subdev, "ACR WPR init complete\n");
234 ver, fwif->acr);
    [all...]
nouveau_nvkm_subdev_pmu_gp10b.c 29 #include <subdev/acr.h>
priv.h 60 const struct nvkm_acr_lsf_func *acr; member in struct:nvkm_pmu_fwif
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_dce3_1_afmt.c 176 const struct radeon_hdmi_acr *acr)
183 HDMI0_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
186 HDMI0_ACR_CTS_32(acr->cts_32khz),
189 HDMI0_ACR_N_32(acr->n_32khz),
193 HDMI0_ACR_CTS_44(acr->cts_44_1khz),
196 HDMI0_ACR_N_44(acr->n_44_1khz),
200 HDMI0_ACR_CTS_48(acr->cts_48khz),
203 HDMI0_ACR_N_48(acr->n_48khz),
radeon_evergreen_hdmi.c 73 const struct radeon_hdmi_acr *acr)
86 HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
90 HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
92 WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr->cts_32khz));
93 WREG32(HDMI_ACR_32_1 + offset, acr->n_32khz);
95 WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr->cts_44_1khz));
96 WREG32(HDMI_ACR_44_1 + offset, acr->n_44_1khz);
98 WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr->cts_48khz));
99 WREG32(HDMI_ACR_48_1 + offset, acr->n_48khz);
radeon_r600_hdmi.c 183 const struct radeon_hdmi_acr *acr)
193 HDMI0_ACR_AUTO_SEND, /* allow hw to sent ACR packets when required */
198 HDMI0_ACR_CTS_32(acr->cts_32khz),
201 HDMI0_ACR_N_32(acr->n_32khz),
205 HDMI0_ACR_CTS_44(acr->cts_44_1khz),
208 HDMI0_ACR_N_44(acr->n_44_1khz),
212 HDMI0_ACR_CTS_48(acr->cts_48khz),
215 HDMI0_ACR_N_48(acr->n_48khz),
  /src/sys/external/bsd/drm2/dist/drm/nouveau/include/nvkm/subdev/
secboot.h 47 struct nvkm_acr *acr; member in struct:nvkm_secboot
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/gsp/
nouveau_nvkm_subdev_gsp_base.c 30 #include <subdev/acr.h>
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/device/
priv.h 8 #include <subdev/acr.h>

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