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    Searched refs:addLiveIn (Results 1 - 25 of 90) sorted by relevancy

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  /src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/
SnippetRepetitor.cpp 76 Loop.MBB->addLiveIn(LoopCounter);
78 Loop.MBB->addLiveIn(Reg);
80 Loop.MBB->addLiveIn(LiveIn);
Assembler.cpp 196 MF.getRegInfo().addLiveIn(Reg);
205 Entry.MBB->addLiveIn(Reg);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsMachineFunction.cpp 80 MF.getRegInfo().addLiveIn(Mips::T9_64);
81 MBB.addLiveIn(Mips::T9_64);
108 MF.getRegInfo().addLiveIn(Mips::T9);
109 MBB.addLiveIn(Mips::T9);
143 MF.getRegInfo().addLiveIn(Mips::V0);
144 MBB.addLiveIn(Mips::V0);
Mips16FrameLowering.cpp 132 MBB.addLiveIn(Reg);
MipsSEFrameLowering.cpp 510 MBB.addLiveIn(ABI.GetEhDataReg(I));
597 MBB.addLiveIn(Mips::COP013);
611 MBB.addLiveIn(Mips::COP014);
622 MBB.addLiveIn(Mips::COP012);
809 MBB.addLiveIn(Reg);
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86IndirectThunks.cpp 97 MF.front().addLiveIn(X86::R11);
217 Entry->addLiveIn(ThunkReg);
239 CallTarget->addLiveIn(ThunkReg);
X86CallLowering.cpp 218 MIRBuilder.getMRI()->addLiveIn(PhysReg);
219 MIRBuilder.getMBB().addLiveIn(PhysReg);
X86FrameLowering.cpp 890 RoundMBB->addLiveIn(FinalReg);
907 LoopMBB->addLiveIn(JoinReg);
920 LoopMBB->addLiveIn(RoundedReg);
942 ContinueMBB->addLiveIn(SizeReg);
1442 MBB.addLiveIn(Establisher);
1502 MBB.addLiveIn(X86::R14);
1707 MBB.addLiveIn(Establisher);
2531 MBB.addLiveIn(Reg);
2567 MBB.addLiveIn(Reg);
2783 allocMBB->addLiveIn(LI)
    [all...]
X86CmovConversion.cpp 679 FalseMBB->addLiveIn(X86::EFLAGS);
680 SinkMBB->addLiveIn(X86::EFLAGS);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SILowerSGPRSpills.cpp 193 EntryBB.addLiveIn(CSIReg.getReg());
285 MBB.addLiveIn(LowestAvailableVGPR);
392 MBB.addLiveIn(SSpill.VGPR);
395 MBB.addLiveIn(Reg);
398 MBB.addLiveIn(Reg);
AMDGPUCallLowering.cpp 151 MIRBuilder.getMBB().addLiveIn(PhysReg);
387 Register LiveInReturn = MF.addLiveIn(TRI->getReturnAddressReg(MF),
444 MF.addLiveIn(PrivateSegmentBufferReg, &AMDGPU::SGPR_128RegClass);
450 MF.addLiveIn(DispatchPtrReg, &AMDGPU::SGPR_64RegClass);
456 MF.addLiveIn(QueuePtrReg, &AMDGPU::SGPR_64RegClass);
465 MRI.addLiveIn(InputPtrReg, VReg);
466 B.getMBB().addLiveIn(InputPtrReg);
473 MF.addLiveIn(DispatchIDReg, &AMDGPU::SGPR_64RegClass);
479 MF.addLiveIn(FlatScratchInitReg, &AMDGPU::SGPR_64RegClass);
595 Register LiveInReturn = MF.addLiveIn(ReturnAddrReg
    [all...]
SIFrameLowering.cpp 178 MF->getRegInfo().addLiveIn(GitPtrLo);
179 MBB.addLiveIn(GitPtrLo);
264 MRI.addLiveIn(FlatScratchInitReg);
265 MBB.addLiveIn(FlatScratchInitReg);
433 OtherBB.addLiveIn(ScratchRsrcReg);
447 MRI.addLiveIn(PreloadedScratchRsrcReg);
448 MBB.addLiveIn(PreloadedScratchRsrcReg);
498 MRI.addLiveIn(PreloadedScratchWaveOffsetReg);
499 MBB.addLiveIn(PreloadedScratchWaveOffsetReg);
600 MF.getRegInfo().addLiveIn(MFI->getImplicitBufferPtrUserSGPR())
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZPostRewrite.cpp 182 RestMBB->addLiveIn(*I);
187 MoveMBB->addLiveIn(SrcReg);
189 MoveMBB->addLiveIn(*I);
SystemZFrameLowering.cpp 195 MBB.addLiveIn(GPR64);
245 MBB.addLiveIn(Reg);
250 MBB.addLiveIn(Reg);
534 I->addLiveIn(SystemZ::R11D);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonCFGOptimizer.cpp 231 LayoutSucc->addLiveIn(NewLI);
  /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
MSP430FrameLowering.cpp 76 I->addLiveIn(MSP430::R4);
196 MBB.addLiveIn(Reg);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
SparcFrameLowering.cpp 352 MBB->addLiveIn(reg - SP::I0_I1 + SP::O0_O1);
358 MBB->addLiveIn(reg - SP::I0 + SP::O0);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
ImplicitNullChecks.cpp 789 MBB->addLiveIn(Reg);
797 NC.getNotNullSucc()->addLiveIn(MO.getReg());
MachineRegisterInfo.cpp 485 EntryMBB->addLiveIn(LiveIns[i].first);
489 EntryMBB->addLiveIn(LiveIns[i].first);
VirtRegMap.cpp 318 MBB->addLiveIn(PhysReg, LaneMask);
353 MBB->addLiveIn(PhysReg);
360 // each MBB's LiveIns set before calling addLiveIn on them.
CallingConvLower.cpp 260 Register VReg = MF.addLiveIn(PReg, RC);
LivePhysRegs.cpp 271 MBB.addLiveIn(Reg);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMCallLowering.cpp 354 MIRBuilder.getMRI()->addLiveIn(PhysReg);
355 MIRBuilder.getMBB().addLiveIn(PhysReg);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
AVRFrameLowering.cpp 111 I->addLiveIn(AVR::R29R28);
257 MBB.addLiveIn(Reg);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64RedundantCopyElimination.cpp 461 MBB->addLiveIn(KnownReg);

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