| /src/external/apache2/llvm/dist/llvm/include/llvm/MC/ |
| MCInstBuilder.h | 32 Inst.addOperand(MCOperand::createReg(Reg));
38 Inst.addOperand(MCOperand::createImm(Val));
44 Inst.addOperand(MCOperand::createSFPImm(Val));
50 Inst.addOperand(MCOperand::createDFPImm(Val));
56 Inst.addOperand(MCOperand::createExpr(Val));
62 Inst.addOperand(MCOperand::createInst(Val));
67 MCInstBuilder &addOperand(const MCOperand &Op) {
68 Inst.addOperand(Op);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/Disassembler/ |
| MipsDisassembler.cpp | 622 MI.addOperand(MCOperand::createImm(tmp));
628 MI.addOperand(MCOperand::createImm(0));
638 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
640 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
642 MI.addOperand(MCOperand::createImm(Imm));
652 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
654 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
656 MI.addOperand(MCOperand::createImm(Imm));
690 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
693 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/Disassembler/ |
| PPCDisassembler.cpp | 68 Inst.addOperand(MCOperand::createImm(SignExtend32<14>(Imm)));
76 Inst.addOperand(MCOperand::createImm(Offset));
87 Inst.addOperand(MCOperand::createReg(Regs[RegNo]));
197 Inst.addOperand(MCOperand::createImm(Imm));
205 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
213 Inst.addOperand(MCOperand::createImm(Imm));
222 Inst.addOperand(MCOperand::createReg(VSRpRegs[RegNo >> 1]));
245 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
256 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp)));
257 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/AsmParser/ |
| PPCAsmParser.cpp | 447 Inst.addOperand(MCOperand::createReg(RRegs[getReg()]));
452 Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()]));
457 Inst.addOperand(MCOperand::createReg(XRegs[getReg()]));
462 Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()]));
481 Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
486 Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
491 Inst.addOperand(MCOperand::createReg(VFRegs[getReg()]));
496 Inst.addOperand(MCOperand::createReg(VRegs[getReg()]));
501 Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()]));
506 Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()]))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCCompound.cpp | 216 CompoundInsn->addOperand(Rt);
217 CompoundInsn->addOperand(L.getOperand(1)); // Immediate
218 CompoundInsn->addOperand(R.getOperand(0)); // Jump target
228 CompoundInsn->addOperand(Rt);
229 CompoundInsn->addOperand(Rs);
230 CompoundInsn->addOperand(R.getOperand(0)); // Jump target.
242 CompoundInsn->addOperand(Rs);
243 CompoundInsn->addOperand(Rt);
244 CompoundInsn->addOperand(R.getOperand(1));
255 CompoundInsn->addOperand(Rs)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| VEAsmPrinter.cpp | 87 SICInst.addOperand(RD);
95 BSICInst.addOperand(R1);
96 BSICInst.addOperand(R2);
98 BSICInst.addOperand(czero);
99 BSICInst.addOperand(czero);
107 LEAInst.addOperand(RD);
109 LEAInst.addOperand(CZero);
110 LEAInst.addOperand(CZero);
111 LEAInst.addOperand(Imm);
119 LEASLInst.addOperand(RD)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMInstrInfo.cpp | 39 NopInst.addOperand(MCOperand::createImm(0));
40 NopInst.addOperand(MCOperand::createImm(ARMCC::AL));
41 NopInst.addOperand(MCOperand::createReg(0));
44 NopInst.addOperand(MCOperand::createReg(ARM::R0));
45 NopInst.addOperand(MCOperand::createReg(ARM::R0));
46 NopInst.addOperand(MCOperand::createImm(ARMCC::AL));
47 NopInst.addOperand(MCOperand::createReg(0));
48 NopInst.addOperand(MCOperand::createReg(0));
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 304 ITInst.addOperand(MCOperand::createImm(ITState.Cond));
305 ITInst.addOperand(MCOperand::createImm(ITState.Mask));
2456 Inst.addOperand(MCOperand::createImm(0));
2458 Inst.addOperand(MCOperand::createImm(CE->getValue()));
2460 Inst.addOperand(MCOperand::createExpr(Expr));
2475 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
2477 Inst.addOperand(MCOperand::createReg(RegNum));
2482 Inst.addOperand(MCOperand::createImm(unsigned(getVPTPred())));
2484 Inst.addOperand(MCOperand::createReg(RegNum));
2501 Inst.addOperand(MCOperand::createReg(RegNum))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonAsmPrinter.cpp | 252 T.addOperand(Inst.getOperand(i));
260 T.addOperand(MCOperand::createExpr(NewHE));
284 Inst.addOperand(Reg);
285 Inst.addOperand(MCOperand::createReg(Hexagon::R0));
286 Inst.addOperand(S16);
293 Inst.addOperand(MCOperand::createExpr(Zero));
300 Inst.addOperand(MCOperand::createExpr(Zero));
307 Inst.addOperand(MCOperand::createExpr(Zero));
314 Inst.addOperand(MCOperand::createExpr(Zero));
321 Inst.addOperand(MCOperand::createExpr(C255))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/Disassembler/ |
| LanaiDisassembler.cpp | 127 Instr.addOperand(MCOperand::createImm(AluOp));
170 Inst.addOperand(MCOperand::createReg(Reg));
179 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register]));
181 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Offset)));
191 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register]));
193 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register]));
203 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register]));
205 Inst.addOperand(MCOperand::createImm(SignExtend32<10>(Offset)));
223 MI.addOperand(MCOperand::createImm(Insn));
230 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Offset)))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/Disassembler/ |
| SystemZDisassembler.cpp | 88 Inst.addOperand(MCOperand::createReg(RegNo));
174 Inst.addOperand(MCOperand::createImm(Imm));
182 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
256 Inst.addOperand(MCOperand::createImm(Value));
296 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
297 Inst.addOperand(MCOperand::createImm(Disp));
306 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
307 Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Disp)));
317 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
318 Inst.addOperand(MCOperand::createImm(Disp))
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 101 MI->addOperand(*MF, MachineOperand::CreateReg(RegNo,
132 MI->addOperand(*MF, MachineOperand::CreateImm(Val));
137 MI->addOperand(*MF, MachineOperand::CreateCImm(Val));
142 MI->addOperand(*MF, MachineOperand::CreateFPImm(Val));
148 MI->addOperand(*MF, MachineOperand::CreateMBB(MBB, TargetFlags));
153 MI->addOperand(*MF, MachineOperand::CreateFI(Idx));
160 MI->addOperand(*MF, MachineOperand::CreateCPI(Idx, Offset, TargetFlags));
166 MI->addOperand(*MF, MachineOperand::CreateTargetIndex(Idx, Offset,
173 MI->addOperand(*MF, MachineOperand::CreateJTI(Idx, TargetFlags));
180 MI->addOperand(*MF, MachineOperand::CreateGA(GV, Offset, TargetFlags))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/Disassembler/ |
| RISCVDisassembler.cpp | 74 Inst.addOperand(MCOperand::createReg(Reg));
85 Inst.addOperand(MCOperand::createReg(Reg));
96 Inst.addOperand(MCOperand::createReg(Reg));
107 Inst.addOperand(MCOperand::createReg(Reg));
118 Inst.addOperand(MCOperand::createReg(Reg));
129 Inst.addOperand(MCOperand::createReg(Reg));
160 Inst.addOperand(MCOperand::createReg(Reg));
171 Inst.addOperand(MCOperand::createReg(Reg));
191 Inst.addOperand(MCOperand::createReg(Reg));
211 Inst.addOperand(MCOperand::createReg(Reg))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVMCInstLower.cpp | 196 OutMI.addOperand(MCOp);
202 OutMI.addOperand(MCOperand::createReg(RISCV::NoRegister));
217 OutMI.addOperand(MCOp);
236 OutMI.addOperand(MCOperand::createImm(
238 OutMI.addOperand(MCOperand::createReg(RISCV::X0));
242 OutMI.addOperand(
244 OutMI.addOperand(MCOperand::createReg(RISCV::X0));
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SIFixVGPRCopies.cpp | 58 MI.addOperand(MF,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/Disassembler/ |
| ARCDisassembler.cpp | 129 Inst.addOperand(MCOperand::createReg(Reg));
164 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(S9)));
183 Inst.addOperand(MCOperand::createImm(Offset));
201 Inst.addOperand(MCOperand::createImm(
213 Inst.addOperand(
230 Inst.addOperand(MCOperand::createImm(LImm));
231 Inst.addOperand(MCOperand::createImm(0));
248 Inst.addOperand(MCOperand::createImm(LImm));
249 Inst.addOperand(MCOperand::createImm(0));
266 Inst.addOperand(MCOperand::createImm((uint32_t)(Insn >> 32)))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | 336 Inst.addOperand(MCOperand::createReg(Register));
365 Inst.addOperand(MCOperand::createReg(Register));
386 Inst.addOperand(MCOperand::createReg(Register));
407 Inst.addOperand(MCOperand::createReg(Register));
428 Inst.addOperand(MCOperand::createReg(Register));
449 Inst.addOperand(MCOperand::createReg(Register));
460 Inst.addOperand(MCOperand::createReg(Register));
489 Inst.addOperand(MCOperand::createReg(Register));
501 Inst.addOperand(MCOperand::createReg(Register));
522 Inst.addOperand(MCOperand::createReg(Register))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/Disassembler/ |
| WebAssemblyDisassembler.cpp | 104 MI.addOperand(MCOperand::createImm(Val));
116 MI.addOperand(
119 MI.addOperand(MCOperand::createImm(static_cast<int64_t>(Val)));
228 MI.addOperand(
231 MI.addOperand(MCOperand::createImm(Val & 0x7f));
240 MI.addOperand(MCOperand::createExpr(Expr));
259 MI.addOperand(MCOperand::createImm(Val & 0x7f));
261 MI.addOperand(
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/Disassembler/ |
| BPFDisassembler.cpp | 107 Inst.addOperand(MCOperand::createReg(Reg));
122 Inst.addOperand(MCOperand::createReg(Reg));
132 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register]));
134 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Offset)));
213 Instr.addOperand(MCOperand::createReg(BPF::R6));
214 Instr.addOperand(Op);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsTargetStreamer.cpp | 173 TmpInst.addOperand(MCOperand::createReg(Reg0));
182 TmpInst.addOperand(MCOperand::createReg(Reg0));
183 TmpInst.addOperand(Op1);
202 TmpInst.addOperand(MCOperand::createImm(Imm1));
203 TmpInst.addOperand(MCOperand::createImm(Imm2));
213 TmpInst.addOperand(MCOperand::createReg(Reg0));
214 TmpInst.addOperand(MCOperand::createReg(Reg1));
215 TmpInst.addOperand(Op2);
231 TmpInst.addOperand(MCOperand::createReg(Reg0));
232 TmpInst.addOperand(MCOperand::createReg(Reg1))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/AsmParser/ |
| HexagonAsmParser.cpp | 384 Inst.addOperand(MCOperand::createReg(getReg()));
389 Inst.addOperand(MCOperand::createExpr(getImm()));
398 Inst.addOperand(MCOperand::createExpr(Expr));
408 Inst.addOperand(MCOperand::createExpr(NewExpr));
543 NewInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create(
549 NewInst.addOperand(I);
620 MCB.addOperand(MCOperand::createImm(0));
653 MCB.addOperand(MCOperand::createInst(SubInst));
1238 TmpInst.addOperand(Rdd);
1239 TmpInst.addOperand(MO1)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/MCTargetDesc/ |
| RISCVAsmBackend.cpp | 155 Res.addOperand(Inst.getOperand(0));
156 Res.addOperand(MCOperand::createReg(RISCV::X0));
157 Res.addOperand(Inst.getOperand(1));
162 Res.addOperand(Inst.getOperand(0));
163 Res.addOperand(MCOperand::createReg(RISCV::X0));
164 Res.addOperand(Inst.getOperand(1));
169 Res.addOperand(MCOperand::createReg(RISCV::X0));
170 Res.addOperand(Inst.getOperand(0));
175 Res.addOperand(MCOperand::createReg(RISCV::X1));
176 Res.addOperand(Inst.getOperand(0))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64AsmPrinter.cpp | 1046 MCInstBuilder(CallOpcode).addOperand(CallTargetMCOp));
1077 MI.addOperand(MCOperand::createReg(DefRegister));
1084 MI.addOperand(Dest);
1104 MOVI.addOperand(MCOperand::createReg(DestReg));
1105 MOVI.addOperand(MCOperand::createImm(0));
1113 FMov.addOperand(MCOperand::createReg(DestReg));
1114 FMov.addOperand(MCOperand::createReg(AArch64::WZR));
1118 FMov.addOperand(MCOperand::createReg(DestReg));
1119 FMov.addOperand(MCOperand::createReg(AArch64::WZR));
1123 FMov.addOperand(MCOperand::createReg(DestReg))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsMCInstLower.cpp | 219 OutMI.addOperand(LowerOperand(MI->getOperand(0)));
244 OutMI.addOperand(MCOperand::createExpr(MipsExpr));
247 OutMI.addOperand(createSub(MI->getOperand(1).getMBB(),
278 OutMI.addOperand(LowerOperand(MO));
286 OutMI.addOperand(MCOperand::createExpr(MipsExpr));
289 OutMI.addOperand(createSub(MI->getOperand(2).getMBB(),
326 OutMI.addOperand(MCOp);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/Disassembler/ |
| SparcDisassembler.cpp | 152 Inst.addOperand(MCOperand::createReg(Reg));
163 Inst.addOperand(MCOperand::createReg(Reg));
175 Inst.addOperand(MCOperand::createReg(Reg));
187 Inst.addOperand(MCOperand::createReg(Reg));
202 Inst.addOperand(MCOperand::createReg(Reg));
213 Inst.addOperand(MCOperand::createReg(Reg));
222 Inst.addOperand(MCOperand::createReg(FCCRegDecoderTable[RegNo]));
231 Inst.addOperand(MCOperand::createReg(ASRRegDecoderTable[RegNo]));
240 Inst.addOperand(MCOperand::createReg(PRRegDecoderTable[RegNo]));
255 Inst.addOperand(MCOperand::createReg(RegisterPair))
[all...] |
