| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZAsmPrinter.cpp | 36 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg()))
40 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg()))
41 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg()))
50 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg()))
54 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg()))
55 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg()))
63 .addReg(MI->getOperand(0).getReg())
64 .addReg(MI->getOperand(1).getReg())
65 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg()))
110 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg())
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| AVRExpandPseudoInsts.cpp | 155 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
156 .addReg(DstLoReg, getKillRegState(DstIsKill))
157 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
160 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
161 .addReg(DstHiReg, getKillRegState(DstIsKill))
162 .addReg(SrcHiReg, getKillRegState(SrcIsKill));
188 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
189 .addReg(DstLoReg, getKillRegState(DstIsKill))
190 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
196 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)
[all...] |
| AVRRelaxMemOperations.cpp | 100 .addReg(Ptr.getReg());
104 .addReg(Ptr.getReg(), RegState::Define)
105 .addReg(Ptr.getReg())
111 .addReg(Ptr.getReg())
112 .addReg(Src.getReg(), getKillRegState(Src.isKill()));
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsExpandPseudo.cpp | 145 BuildMI(loop1MBB, DL, TII->get(LL), Scratch).addReg(Ptr).addImm(0);
147 .addReg(Scratch)
148 .addReg(Mask);
150 .addReg(Scratch2).addReg(ShiftCmpVal).addMBB(sinkMBB);
158 .addReg(Scratch, RegState::Kill)
159 .addReg(Mask2);
161 .addReg(Scratch, RegState::Kill)
162 .addReg(ShiftNewVal);
164 .addReg(Scratch, RegState::Kill
[all...] |
| MipsFastISel.cpp | 221 return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
226 return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
332 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg);
369 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
372 emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
381 emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
396 emitInst(Mips::MTC1, DestReg).addReg(TempReg);
404 emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1)
[all...] |
| MipsMachineFunction.cpp | 89 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
90 .addReg(Mips::T9_64);
91 BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
103 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
118 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
119 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
146 .addReg(Mips::V0).addReg(Mips::T9);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86InstrBuilder.h | 127 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0);
144 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0);
149 return MIB.addImm(1).addReg(0).add(Offset).addReg(0);
159 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
167 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
168 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVExpandAtomicPseudoInsts.cpp | 234 .addReg(AddrReg);
240 .addReg(DestReg)
241 .addReg(IncrReg);
243 .addReg(ScratchReg)
248 .addReg(AddrReg)
249 .addReg(ScratchReg);
251 .addReg(ScratchReg)
252 .addReg(RISCV::X0)
268 .addReg(OldValReg)
269 .addReg(NewValReg)
[all...] |
| /src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/PowerPC/ |
| Target.cpp | 62 .addReg(Reg)
104 MCInstBuilder(PPC::MTVSRD).addReg(Reg).addReg(ScratchImmReg)};
110 MCInstBuilder(PPC::MTVRD).addReg(Reg).addReg(ScratchImmReg)};
114 .addReg(Reg)
115 .addReg(ScratchImmReg)
116 .addReg(ScratchImmReg)};
119 MCInstBuilder(PPC::MTVSRD).addReg(Reg).addReg(ScratchImmReg)}
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| BPFInstrInfo.cpp | 37 .addReg(SrcReg, getKillRegState(KillSrc));
40 .addReg(SrcReg, getKillRegState(KillSrc));
79 .addReg(ScratchReg, RegState::Define).addReg(SrcReg)
82 .addReg(ScratchReg, RegState::Kill).addReg(DstReg)
93 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset);
95 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMAsmPrinter.cpp | 185 .addReg(TIP.first)
188 .addReg(0));
1025 .addReg(0));
1330 .addReg(MI->getOperand(0).getReg())
1334 .addReg(MI->getOperand(3).getReg()));
1346 .addReg(MI->getOperand(0).getReg())
1350 .addReg(MI->getOperand(3).getReg()));
1357 .addReg(ARM::LR)
1358 .addReg(ARM::PC)
1361 .addReg(0
[all...] |
| MVETailPredUtils.h | 97 MIB.addReg(ARM::NoRegister);
105 MIB.addReg(ARM::NoRegister);
106 MIB.addReg(ARM::CPSR, RegState::Define);
114 MIB.addReg(ARM::CPSR);
139 MIB.addReg(0);
142 MIB.addReg(ARM::CPSR);
145 MIB.addReg(0);
162 MIB.addReg(ARM::NoRegister);
170 MIB.addReg(ARM::CPSR);
|
| ARMFrameLowering.cpp | 378 .addReg(Reg, RegState::Kill)
383 .addReg(Reg, RegState::Kill)
393 .addReg(Reg, RegState::Kill)
398 .addReg(Reg, RegState::Kill)
408 .addReg(Reg, RegState::Kill)
629 .addReg(ARM::R4, RegState::Implicit)
639 .addReg(ARM::R12, RegState::Kill)
640 .addReg(ARM::R4, RegState::Implicit)
646 .addReg(ARM::SP, RegState::Kill)
647 .addReg(ARM::R4, RegState::Kill
[all...] |
| Thumb1InstrInfo.cpp | 29 .addReg(ARM::R8)
30 .addReg(ARM::R8)
32 .addReg(0);
53 .addReg(SrcReg, getKillRegState(KillSrc))
63 .addReg(SrcReg, getKillRegState(KillSrc))
71 .addReg(SrcReg, getKillRegState(KillSrc));
74 .addReg(DestReg, getDefRegState(true));
98 .addReg(SrcReg, getKillRegState(isKill))
|
| /src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/Mips/ |
| Target.cpp | 90 .addReg(Reg)
91 .addReg(ZeroReg)
103 .addReg(Reg)
104 .addReg(ZeroReg)
108 .addReg(Reg)
109 .addReg(Reg)
114 .addReg(Reg)
122 .addReg(Reg)
123 .addReg(ZeroReg)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| VEFrameLowering.cpp | 153 .addReg(VE::SX11)
156 .addReg(VE::SX9);
158 .addReg(VE::SX11)
161 .addReg(VE::SX10);
165 .addReg(VE::SX11)
168 .addReg(VE::SX15);
170 .addReg(VE::SX11)
173 .addReg(VE::SX16);
177 .addReg(VE::SX11)
180 .addReg(VE::SX17)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| LanaiFrameLowering.cpp | 79 .addReg(Src)
114 .addReg(Lanai::FP)
115 .addReg(Lanai::SP)
123 .addReg(Lanai::SP)
131 .addReg(Lanai::SP)
187 .addReg(Lanai::FP)
192 .addReg(Lanai::FP)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 71 .addReg(FrameReg)
77 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
78 .addReg(FrameReg)
84 .addReg(FrameReg)
107 .addReg(FrameReg)
108 .addReg(ScratchOffset, RegState::Kill)
113 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
114 .addReg(FrameReg)
115 .addReg(ScratchOffset, RegState::Kill)
120 .addReg(FrameReg
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 797 MIB.addReg(MustSaveCRs[0], RegState::Kill);
802 MIB.addReg(CRfield, RegState::ImplicitKill);
811 .addReg(TempReg, getKillRegState(true))
813 .addReg(SPReg);
825 .addReg(FPReg)
827 .addReg(SPReg);
830 .addReg(PPC::R30)
832 .addReg(SPReg);
835 .addReg(BPReg)
837 .addReg(SPReg)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/ |
| ARCExpandPseudos.cpp | 66 .addReg(SI.getOperand(1).getReg())
70 .addReg(SI.getOperand(0).getReg())
71 .addReg(AddrReg)
|
| ARCRegisterInfo.cpp | 51 .addReg(BaseReg)
76 .addReg(BaseReg, RegState::Define)
77 .addReg(FrameReg)
94 .addReg(BaseReg, KillState)
107 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
108 .addReg(BaseReg, KillState)
116 .addReg(Reg, RegState::Define)
117 .addReg(FrameReg)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SIFrameLowering.cpp | 34 LiveRegs.addReg(CSRegs[i]);
132 LiveRegs.addReg(SpillReg);
172 .addReg(TargetReg, RegState::ImplicitDefine);
181 .addReg(GitPtrLo);
248 .addReg(FlatScrInit)
256 .addReg(FlatScrInitHi)
275 .addReg(FlatScrInitLo)
276 .addReg(ScratchWaveOffsetReg);
278 .addReg(FlatScrInitHi)
281 addReg(FlatScrInitLo)
[all...] |
| AMDGPUInstructionSelector.cpp | 160 .addReg(SrcReg);
163 .addReg(MaskedReg);
244 .addReg(Reg, 0, ComposedSubIdx);
380 .addReg(CarryReg, RegState::Kill)
388 .addReg(DstLo)
390 .addReg(DstHi)
428 .addReg(I.getOperand(4).getReg());
438 .addReg(AMDGPU::SCC);
497 .addReg(SrcReg, 0, SubReg);
526 MIB.addReg(Src.getReg(), getUndefRegState(Src.isUndef()))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64SIMDInstrOpt.cpp | 450 .addReg(SrcReg2, Src2IsKill)
454 .addReg(SrcReg0, Src0IsKill)
455 .addReg(SrcReg1, Src1IsKill)
456 .addReg(DupDest, Src2IsKill);
462 .addReg(SrcReg1, Src1IsKill)
466 .addReg(SrcReg0, Src0IsKill)
467 .addReg(DupDest, Src1IsKill);
566 .addReg(StReg[0])
567 .addReg(StReg[1]);
569 .addReg(StReg[0], StRegKill[0]
[all...] |
| AArch64AsmPrinter.cpp | 388 .addReg(AArch64::X16)
389 .addReg(Reg)
395 .addReg(AArch64::W16)
396 .addReg(IsShort ? AArch64::X20 : AArch64::X9)
397 .addReg(AArch64::X16)
403 .addReg(AArch64::XZR)
404 .addReg(AArch64::X16)
405 .addReg(Reg)
418 MCInstBuilder(AArch64::RET).addReg(AArch64::LR), *STI);
423 .addReg(AArch64::X16
[all...] |
