| /src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| RegisterBankEmitter.cpp | 73 void addRegisterClass(const CodeGenRegisterClass *RC) {
295 Bank.addRegisterClass(RC);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonISelLoweringHVX.cpp | 30 addRegisterClass(MVT::v64i8, &Hexagon::HvxVRRegClass);
31 addRegisterClass(MVT::v32i16, &Hexagon::HvxVRRegClass);
32 addRegisterClass(MVT::v16i32, &Hexagon::HvxVRRegClass);
33 addRegisterClass(MVT::v128i8, &Hexagon::HvxWRRegClass);
34 addRegisterClass(MVT::v64i16, &Hexagon::HvxWRRegClass);
35 addRegisterClass(MVT::v32i32, &Hexagon::HvxWRRegClass);
44 addRegisterClass(MVT::v16i1, &Hexagon::HvxQRRegClass);
45 addRegisterClass(MVT::v32i1, &Hexagon::HvxQRRegClass);
46 addRegisterClass(MVT::v64i1, &Hexagon::HvxQRRegClass);
48 addRegisterClass(MVT::v128i8, &Hexagon::HvxVRRegClass)
[all...] |
| HexagonISelLowering.cpp | 1469 addRegisterClass(MVT::i1, &Hexagon::PredRegsRegClass);
1470 addRegisterClass(MVT::v2i1, &Hexagon::PredRegsRegClass); // bbbbaaaa
1471 addRegisterClass(MVT::v4i1, &Hexagon::PredRegsRegClass); // ddccbbaa
1472 addRegisterClass(MVT::v8i1, &Hexagon::PredRegsRegClass); // hgfedcba
1473 addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass);
1474 addRegisterClass(MVT::v2i16, &Hexagon::IntRegsRegClass);
1475 addRegisterClass(MVT::v4i8, &Hexagon::IntRegsRegClass);
1476 addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass);
1477 addRegisterClass(MVT::v8i8, &Hexagon::DoubleRegsRegClass);
1478 addRegisterClass(MVT::v4i16, &Hexagon::DoubleRegsRegClass)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelLowering.cpp | 57 addRegisterClass(MVT::i32, &WebAssembly::I32RegClass);
58 addRegisterClass(MVT::i64, &WebAssembly::I64RegClass);
59 addRegisterClass(MVT::f32, &WebAssembly::F32RegClass);
60 addRegisterClass(MVT::f64, &WebAssembly::F64RegClass);
62 addRegisterClass(MVT::v16i8, &WebAssembly::V128RegClass);
63 addRegisterClass(MVT::v8i16, &WebAssembly::V128RegClass);
64 addRegisterClass(MVT::v4i32, &WebAssembly::V128RegClass);
65 addRegisterClass(MVT::v4f32, &WebAssembly::V128RegClass);
66 addRegisterClass(MVT::v2i64, &WebAssembly::V128RegClass);
67 addRegisterClass(MVT::v2f64, &WebAssembly::V128RegClass)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SIISelLowering.cpp | 78 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
79 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
81 addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass);
82 addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass);
84 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass);
89 addRegisterClass(MVT::f64, V64RegClass);
90 addRegisterClass(MVT::v2f32, V64RegClass);
92 addRegisterClass(MVT::v3i32, &AMDGPU::SGPR_96RegClass);
93 addRegisterClass(MVT::v3f32, TRI->getVGPRClassForBitWidth(96));
95 addRegisterClass(MVT::v2i64, &AMDGPU::SGPR_128RegClass)
[all...] |
| R600ISelLowering.cpp | 31 addRegisterClass(MVT::f32, &R600::R600_Reg32RegClass);
32 addRegisterClass(MVT::i32, &R600::R600_Reg32RegClass);
33 addRegisterClass(MVT::v2f32, &R600::R600_Reg64RegClass);
34 addRegisterClass(MVT::v2i32, &R600::R600_Reg64RegClass);
35 addRegisterClass(MVT::v4f32, &R600::R600_Reg128RegClass);
36 addRegisterClass(MVT::v4i32, &R600::R600_Reg128RegClass);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 61 addRegisterClass(MVT::i64, &BPF::GPRRegClass);
63 addRegisterClass(MVT::i32, &BPF::GPR32RegClass);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| VEISelLowering.cpp | 81 addRegisterClass(MVT::i32, &VE::I32RegClass);
82 addRegisterClass(MVT::i64, &VE::I64RegClass);
83 addRegisterClass(MVT::f32, &VE::F32RegClass);
84 addRegisterClass(MVT::f64, &VE::I64RegClass);
85 addRegisterClass(MVT::f128, &VE::F128RegClass);
89 addRegisterClass(VecVT, &VE::V64RegClass);
90 addRegisterClass(MVT::v256i1, &VE::VMRegClass);
91 addRegisterClass(MVT::v512i1, &VE::VM512RegClass);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 68 addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
71 addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
89 addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
127 addRegisterClass(MVT::f16, &Mips::MSA128HRegClass);
172 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
177 addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
179 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
319 addRegisterClass(Ty, RC);
373 addRegisterClass(Ty, RC);
|
| Mips16ISelLowering.cpp | 125 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 360 addRegisterClass(MVT::i1, &NVPTX::Int1RegsRegClass);
361 addRegisterClass(MVT::i16, &NVPTX::Int16RegsRegClass);
362 addRegisterClass(MVT::i32, &NVPTX::Int32RegsRegClass);
363 addRegisterClass(MVT::i64, &NVPTX::Int64RegsRegClass);
364 addRegisterClass(MVT::f32, &NVPTX::Float32RegsRegClass);
365 addRegisterClass(MVT::f64, &NVPTX::Float64RegsRegClass);
366 addRegisterClass(MVT::f16, &NVPTX::Float16RegsRegClass);
367 addRegisterClass(MVT::v2f16, &NVPTX::Float16x2RegsRegClass);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 1422 addRegisterClass(MVT::i32, &SP::IntRegsRegClass);
1424 addRegisterClass(MVT::f32, &SP::FPRegsRegClass);
1425 addRegisterClass(MVT::f64, &SP::DFPRegsRegClass);
1426 addRegisterClass(MVT::f128, &SP::QFPRegsRegClass);
1429 addRegisterClass(MVT::i64, &SP::I64RegsRegClass);
1433 addRegisterClass(MVT::v2i32, &SP::IntPairRegClass);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 245 addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass);
246 addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass);
249 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
250 addRegisterClass(MVT::bf16, &AArch64::FPR16RegClass);
251 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
252 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
253 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
257 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass);
258 addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass);
283 addRegisterClass(MVT::nxv2i1, &AArch64::PPRRegClass)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 149 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
152 addRegisterClass(MVT::f32, &PPC::GPRCRegClass);
155 addRegisterClass(MVT::f64, &PPC::SPERCRegClass);
157 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
158 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
277 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
684 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
881 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
882 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
883 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/ |
| ARCISelLowering.cpp | 75 addRegisterClass(MVT::i32, &ARC::GPR32RegClass);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 87 addRegisterClass(MVT::i32, &SystemZ::GRX32BitRegClass);
89 addRegisterClass(MVT::i32, &SystemZ::GR32BitRegClass);
90 addRegisterClass(MVT::i64, &SystemZ::GR64BitRegClass);
93 addRegisterClass(MVT::f32, &SystemZ::VR32BitRegClass);
94 addRegisterClass(MVT::f64, &SystemZ::VR64BitRegClass);
96 addRegisterClass(MVT::f32, &SystemZ::FP32BitRegClass);
97 addRegisterClass(MVT::f64, &SystemZ::FP64BitRegClass);
100 addRegisterClass(MVT::f128, &SystemZ::VR128BitRegClass);
102 addRegisterClass(MVT::f128, &SystemZ::FP128BitRegClass);
105 addRegisterClass(MVT::v16i8, &SystemZ::VR128BitRegClass)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| AVRISelLowering.cpp | 39 addRegisterClass(MVT::i8, &AVR::GPR8RegClass);
40 addRegisterClass(MVT::i16, &AVR::DREGSRegClass);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 49 addRegisterClass(MVT::i8, &MSP430::GR8RegClass);
50 addRegisterClass(MVT::i16, &MSP430::GR16RegClass);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| M68kISelLowering.cpp | 58 addRegisterClass(MVT::i8, &M68k::DR8RegClass);
59 addRegisterClass(MVT::i16, &M68k::XR16RegClass);
60 addRegisterClass(MVT::i32, &M68k::XR32RegClass);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 182 addRegisterClass(MVT::i8, &X86::GR8RegClass);
183 addRegisterClass(MVT::i16, &X86::GR16RegClass);
184 addRegisterClass(MVT::i32, &X86::GR32RegClass);
186 addRegisterClass(MVT::i64, &X86::GR64RegClass);
555 addRegisterClass(MVT::f32, Subtarget.hasAVX512() ? &X86::FR32XRegClass
557 addRegisterClass(MVT::f64, Subtarget.hasAVX512() ? &X86::FR64XRegClass
594 addRegisterClass(MVT::f32, &X86::FR32RegClass);
596 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
626 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
627 addRegisterClass(MVT::f32, &X86::RFP32RegClass)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| LanaiISelLowering.cpp | 77 addRegisterClass(MVT::i32, &Lanai::GPRRegClass);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 227 addRegisterClass(VT, &ARM::DPRRegClass);
232 addRegisterClass(VT, &ARM::DPairRegClass);
260 addRegisterClass(VT, &ARM::MQPRRegClass);
326 addRegisterClass(VT, &ARM::MQPRRegClass);
394 addRegisterClass(VT, &ARM::MQPRRegClass);
438 addRegisterClass(VT, &ARM::VCCRRegClass);
736 addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
738 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
742 addRegisterClass(MVT::f32, &ARM::SPRRegClass);
743 addRegisterClass(MVT::f64, &ARM::DPRRegClass)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 77 addRegisterClass(MVT::i32, &XCore::GRRegsRegClass);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVISelLowering.cpp | 84 addRegisterClass(XLenVT, &RISCV::GPRRegClass);
87 addRegisterClass(MVT::f16, &RISCV::FPR16RegClass);
89 addRegisterClass(MVT::f32, &RISCV::FPR32RegClass);
91 addRegisterClass(MVT::f64, &RISCV::FPR64RegClass);
124 addRegisterClass(VT, RC);
149 addRegisterClass(VT, TRI.getRegClass(RCID));
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| TargetLowering.h | 2148 void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
|
