| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsInstructionSelector.cpp | 279 .addUse(TiedDest)
334 .addUse(PseudoMULTuReg);
363 .addUse(Mips::ZERO)
376 .addUse(I.getOperand(2).getReg())
384 .addUse(I.getOperand(0).getReg())
385 .addUse(JTIndex);
393 .addUse(DestAddress)
405 .addUse(DestTmp)
406 .addUse(MF.getInfo<MipsFunctionInfo>()
414 .addUse(Dest)
[all...] |
| MipsISelLowering.cpp | 4752 .addUse(Address)
4754 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Dest).addUse(Temp);
4764 .addUse(Address)
4766 .addUse(Undef);
4769 .addUse(Address)
4771 .addUse(LoadHalf);
4772 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Dest).addUse(LoadFull);
4799 .addUse(Address)
4801 BuildMI(*BB, I, DL, TII->get(Mips::FILL_D)).addDef(Dest).addUse(Temp);
4808 .addUse(Address
[all...] |
| MipsSEISelDAGToDAG.cpp | 135 .addUse(Mips::RA_64, RegState::Undef)
136 .addUse(Mips::ZERO_64);
138 MIB.addUse(Mips::AT_64, RegState::Implicit);
143 .addUse(Mips::RA, RegState::Undef)
144 .addUse(Mips::ZERO);
148 .addUse(Mips::SP)
151 MIB.addUse(Mips::AT, RegState::Implicit);
|
| MipsCallLowering.cpp | 255 MIB.addUse(PhysReg, RegState::Implicit);
543 MIB.addUse(CalleeReg);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64SpeculationHardening.cpp | 233 .addUse(MisspeculatingTaintReg)
234 .addUse(AArch64::XZR)
371 .addUse(AArch64::SP)
377 .addUse(AArch64::XZR)
378 .addUse(AArch64::XZR)
394 .addUse(AArch64::SP)
400 .addUse(TmpReg, RegState::Kill | RegState::Renamable)
401 .addUse(MisspeculatingTaintReg, RegState::Kill)
406 .addUse(TmpReg, RegState::Kill)
454 .addUse(Reg)
[all...] |
| AArch64ExpandPseudoInsts.cpp | 305 .addUse(AArch64::WZR)
306 .addUse(AArch64::WZR)
313 .addUse(StatusReg, RegState::Kill)
314 .addUse(StatusReg, RegState::Kill)
317 .addUse(StatusReg, getKillRegState(StatusDead))
611 BuildMI(LoopBB, DL, TII->get(AArch64::CBNZX)).addUse(SizeReg).addMBB(LoopBB);
711 .addUse(CtxReg)
712 .addUse(BaseReg)
728 .addUse(BaseReg)
733 .addUse(AArch64::X16
[all...] |
| AArch64LowerHomogeneousPrologEpilog.cpp | 313 .addUse(AArch64::SP)
329 .addUse(AArch64::LR)
557 .addUse(AArch64::SP)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPULegalizerInfo.cpp | 1967 .addUse(Hi)
1968 .addUse(Const0.getReg(0))
1969 .addUse(Const1.getReg(0));
2041 .addUse(CvtHi.getReg(0))
2042 .addUse(ThirtyTwo.getReg(0));
2203 .addUse(MulVal.getReg(0))
2211 .addUse(TrigVal)
2510 .addUse(PtrReg)
2511 .addUse(PackedVal)
2560 .addUse(Log.getReg(0)
[all...] |
| AMDGPURegisterBankInfo.cpp | 664 .addUse(Reg);
1494 .addUse(RSrc) // rsrc
1495 .addUse(VIndex) // vindex
1496 .addUse(VOffset) // voffset
1497 .addUse(SOffset) // soffset
1797 .addUse(VData);
1800 MIB.addUse(VOffset);
1802 MIB.addUse(RSrc)
1803 .addUse(SOffset)
1826 .addUse(SrcReg)
[all...] |
| SIFormMemoryClauses.cpp | 392 Kill.addUse(Reg, std::get<0>(Op), std::get<1>(Op));
|
| AMDGPUCallLowering.cpp | 79 MIB.addUse(PhysReg, RegState::Implicit);
212 MIB.addUse(PhysReg, RegState::Implicit);
377 Ret.addUse(ReturnAddrVReg);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMInstructionSelector.cpp | 581 .addUse(LHSReg)
582 .addUse(RHSReg)
600 .addUse(PrevRes)
778 .addUse(CondReg)
794 .addUse(TrueReg)
795 .addUse(FalseReg)
888 .addUse(AndResult)
938 .addUse(SrcReg)
1109 .addUse(OriginalValue)
|
| ARMCallLowering.cpp | 121 MIB.addUse(PhysReg, RegState::Implicit);
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| MachineIRBuilder.cpp | 224 return buildInstr(TargetOpcode::G_BRINDIRECT).addUse(Tgt);
233 .addUse(TablePtr)
235 .addUse(IndexReg);
806 .addUse(Addr)
807 .addUse(CmpVal)
808 .addUse(NewVal)
831 .addUse(Addr)
832 .addUse(CmpVal)
833 .addUse(NewVal)
|
| RegBankSelect.cpp | 166 .addUse(Src);
198 MergeBuilder.addUse(SrcReg);
207 UnMergeBuilder.addUse(MO.getReg());
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| AArch64InstructionSelector.cpp | 939 .addUse(SrcReg)
1702 Shl.addUse(Src2Reg);
1789 .addUse(ArgsAddrReg)
1790 .addUse(ListReg)
1817 auto MovI = MIB.buildInstr(AArch64::MOVKXi).addDef(DstReg).addUse(SrcReg);
2483 .addUse(SrcReg, 0, Offset == 0 ? AArch64::sube64 : AArch64::subo64);
2546 .addUse(I.getOperand(2).getReg())
2653 IsStore ? NewInst.addUse(ValReg) : NewInst.addDef(ValReg);
2698 .addUse(LdReg)
2926 .addUse(SrcReg
[all...] |
| AArch64LegalizerInfo.cpp | 1059 .addUse(CTPOP.getReg(0));
1112 .addUse(DesiredI->getOperand(0).getReg())
1114 .addUse(DesiredI->getOperand(1).getReg())
1117 .addUse(NewI->getOperand(0).getReg())
1119 .addUse(NewI->getOperand(1).getReg())
|
| AArch64CallLowering.cpp | 274 MIB.addUse(PhysReg, RegState::Implicit);
457 MIB.addUse(AArch64::X21, RegState::Implicit);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| VEInstrInfo.cpp | 763 BuildMI(*MBB, MI, DL, MCID).addDef(VMXu).addUse(VMYu).addUse(VMZu);
764 BuildMI(*MBB, MI, DL, MCID).addDef(VMXl).addUse(VMYl).addUse(VMZl);
768 BuildMI(*MBB, MI, DL, MCID).addDef(VMXu).addUse(VMYu);
769 BuildMI(*MBB, MI, DL, MCID).addDef(VMXl).addUse(VMYl);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86CallLowering.cpp | 109 MIB.addUse(PhysReg, RegState::Implicit);
348 MIB.addUse(X86::AL, RegState::Implicit);
|
| X86FrameLowering.cpp | 1368 .addUse(MachineFramePtr)
1514 .addUse(X86::RSP)
1516 .addUse(X86::NoRegister)
1518 .addUse(X86::NoRegister)
1521 .addUse(X86::RSP)
2044 .addUse(MachineFramePtr)
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/IR/ |
| Value.h | 514 void addUse(Use &U) { U.addToList(&UseList); }
875 if (V) V->addUse(*this);
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 123 const MachineInstrBuilder &addUse(Register RegNo, unsigned Flags = 0,
126 "Misleading addUse defines register, use addReg instead.");
|
| SelectionDAGNodes.h | 1044 void addUse(SDUse &U) { U.addToList(&UseList); }
1186 if (V.getNode()) V.getNode()->addUse(*this);
1191 V.getNode()->addUse(*this);
1197 if (N) N->addUse(*this);
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| MachineIRBuilder.h | 147 MIB.addUse(Reg);
150 MIB.addUse(SrcMIB->getOperand(0).getReg());
|
