1 /* $NetBSD: umcpmio_hid_reports.h,v 1.3 2025/11/29 18:39:14 brad Exp $ */ 2 3 /* 4 * Copyright (c) 2024 Brad Spencer <brad (at) anduin.eldar.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _UMCPMIO_HID_REPORTS_H_ 20 #define _UMCPMIO_HID_REPORTS_H_ 21 22 #include <sys/types.h> 23 24 /* 25 * It is nice that all HID reports want a 64 byte request and return a 26 * 64 byte response. 27 */ 28 29 #define UMCPMIO_REQ_BUFFER_SIZE 64 30 #define UMCPMIO_RES_BUFFER_SIZE 64 31 32 #define MCP2210_REQ_BUFFER_SIZE UMCPMIO_REQ_BUFFER_SIZE 33 #define MCP2210_RES_BUFFER_SIZE UMCPMIO_RES_BUFFER_SIZE 34 35 /* MCP-2210 stuff */ 36 37 #define MCP2210_CMD_STATUS 0x10 38 #define MCP2210_CMD_SPI_CANCEL 0x11 39 #define MCP2210_CMD_GET_GP6_EVENTS 0x12 40 #define MCP2210_CMD_GET_GPIO_SRAM 0x20 41 #define MCP2210_CMD_SET_GPIO_SRAM 0x21 42 #define MCP2210_CMD_SET_GPIO_VAL_SRAM 0x30 43 #define MCP2210_CMD_GET_GPIO_VAL_SRAM 0x31 44 #define MCP2210_CMD_SET_GPIO_DIR_SRAM 0x32 45 #define MCP2210_CMD_GET_GPIO_DIR_SRAM 0x33 46 #define MCP2210_CMD_SET_SPI_SRAM 0x40 47 #define MCP2210_CMD_GET_SPI_SRAM 0x41 48 #define MCP2210_CMD_SPI_TRANSFER 0x42 49 #define MCP2210_CMD_READ_EEPROM 0x50 50 #define MCP2210_CMD_WRITE_EEPROM 0x51 51 #define MCP2210_CMD_SET_NVRAM 0x60 52 #define MCP2210_CMD_GET_NVRAM 0x61 53 #define MCP2210_CMD_SEND_PASSWORD 0x70 54 #define MCP2210_CMD_SPI_BUS_RELEASE 0x80 55 56 #define UMCPMIO_CMD_COMPLETE_OK 0x00 57 58 #define MCP2210_CMD_COMPLETE_OK 0x00 59 #define MCP2210_CMD_SPI_BUS_UNAVAIL 0xF7 60 #define MCP2210_CMD_USB_TRANSFER_IP 0xF8 61 #define MCP2210_CMD_SPI_TRANSFER_IP MCP2210_CMD_USB_TRANSFER_IP 62 #define MCP2210_CMD_UNKNOWN 0xF9 63 #define MCP2210_CMD_EEPROM_FAIL 0xFA 64 #define MCP2210_CMD_EEPROM_LOCKED 0xFB 65 #define MCP2210_CMD_ACCESS_REJECTED 0xFC 66 #define MCP2210_CMD_ACCESS_DENIED 0xFD 67 #define MCP2210_CMD_BLOCKED_ACCESS MCP2210_CMD_EEPROM_LOCKED 68 69 struct mcp2210_status_req { 70 uint8_t cmd; /* MCP2210_CMD_STATUS */ 71 uint8_t reserved[63]; 72 }; 73 74 #define MCP2221_I2C_SPEED_SET 0x20 75 #define MCP2221_I2C_SPEED_BUSY 0x21 76 #define MCP2221_ENGINE_T1_MASK_NACK 0x40 77 78 struct mcp2210_status_res { 79 uint8_t cmd; 80 uint8_t completion; 81 uint8_t spi_bus_release; 82 uint8_t spi_bus_owner; 83 uint8_t attempted_password_tries; 84 uint8_t password_guessed; 85 uint8_t dontcare[58]; 86 }; 87 88 struct mcp2210_cancel_spi_req { 89 uint8_t cmd; /* MCP2210_CMD_SPI_CANCEL */ 90 uint8_t reserved[63]; 91 }; 92 93 struct mcp2210_cancel_spi_res { 94 uint8_t cmd; 95 uint8_t completion; 96 uint8_t spi_bus_release; 97 uint8_t spi_bus_owner; 98 uint8_t attempted_password_tries; 99 uint8_t password_guessed; 100 uint8_t dontcare[58]; 101 }; 102 103 #define MCP2210_COUNTER_RESET 0x00 104 #define MCP2210_COUNTER_RETAIN 0xff 105 106 struct mcp2210_get_gp6_events_req { 107 uint8_t cmd; /* MCP2210_CMD_GET_GP6_EVENTS */ 108 uint8_t reset_counter; 109 uint8_t reserved[62]; 110 }; 111 112 struct mcp2210_get_gp6_events_res { 113 uint8_t cmd; 114 uint8_t completion; 115 uint8_t dontcare[2]; 116 uint8_t counter_lsb; 117 uint8_t counter_msb; 118 uint8_t dontcare2[58]; 119 }; 120 121 struct mcp2210_get_gpio_sram_req { 122 uint8_t cmd; /* MCP2210_CMD_GET_GPIO_SRAM */ 123 uint8_t reserved[63]; 124 }; 125 126 #define MCP2210_PIN_IS_GPIO 0x00 127 #define MCP2210_PIN_IS_ALT0 0x01 128 #define MCP2210_PIN_IS_DED 0x02 129 130 #define MCP2210_COUNTER_OFF 0x00 131 #define MCP2210_COUNTER_FALLING_EDGE 0x01 132 #define MCP2210_COUNTER_RISING_EDGE 0x02 133 #define MCP2210_COUNTER_LOW_PULSE 0x03 134 #define MCP2210_COUNTER_HIGH_PULSE 0x04 135 136 struct mcp2210_get_gpio_sram_res { 137 uint8_t cmd; 138 uint8_t completion; 139 uint8_t dontcare[2]; 140 #define MCP2210_GPIO_SRAM_GP0 4 141 uint8_t gp0_designation; 142 uint8_t gp1_designation; 143 uint8_t gp2_designation; 144 uint8_t gp3_designation; 145 uint8_t gp4_designation; 146 uint8_t gp5_designation; 147 uint8_t gp6_designation; 148 uint8_t gp7_designation; 149 uint8_t gp8_designation; 150 uint8_t default_output_lsb; 151 uint8_t default_output_msb; 152 uint8_t default_direction_lsb; 153 uint8_t default_direction_msb; 154 uint8_t other_settings; 155 uint8_t nvram_protection; 156 uint8_t dontcare2[45]; 157 }; 158 159 struct mcp2210_set_gpio_sram_req { 160 uint8_t cmd; /* MCP2210_CMD_SET_GPIO_SRAM */ 161 uint8_t reserved[3]; 162 uint8_t gp0_designation; 163 uint8_t gp1_designation; 164 uint8_t gp2_designation; 165 uint8_t gp3_designation; 166 uint8_t gp4_designation; 167 uint8_t gp5_designation; 168 uint8_t gp6_designation; 169 uint8_t gp7_designation; 170 uint8_t gp8_designation; 171 uint8_t default_output_lsb; 172 uint8_t default_output_msb; 173 uint8_t default_direction_lsb; 174 uint8_t default_direction_msb; 175 uint8_t other_settings; 176 uint8_t reserved2[46]; 177 }; 178 179 struct mcp2210_set_gpio_sram_res { 180 uint8_t cmd; 181 uint8_t completion; 182 uint8_t dontcare[62]; 183 }; 184 185 struct mcp2210_set_spi_sram_req { 186 uint8_t cmd; /* MCP2210_CMD_SET_SPI_SRAM */ 187 uint8_t reserved[3]; 188 uint8_t bit_rate_byte_3; /* lsb */ 189 uint8_t bit_rate_byte_2; 190 uint8_t bit_rate_byte_1; 191 uint8_t bit_rate_byte_0; /* msb */ 192 uint8_t idle_cs_value_lsb; 193 uint8_t idle_cs_value_msb; 194 uint8_t active_cs_value_lsb; 195 uint8_t active_cs_value_msb; 196 uint8_t cs_to_data_delay_lsb; 197 uint8_t cs_to_data_delay_msb; 198 uint8_t lb_to_cs_deassert_delay_lsb; 199 uint8_t lb_to_cs_deassert_delay_msb; 200 uint8_t delay_between_bytes_lsb; 201 uint8_t delay_between_bytes_msb; 202 uint8_t bytes_per_spi_transaction_lsb; 203 uint8_t bytes_per_spi_transaction_msb; 204 uint8_t spi_mode; 205 uint8_t dontcare[43]; 206 }; 207 208 struct mcp2210_set_spi_sram_res { 209 uint8_t cmd; 210 uint8_t completion; 211 uint8_t dontcare[2]; 212 uint8_t bit_rate_byte_3; /* lsb */ 213 uint8_t bit_rate_byte_2; 214 uint8_t bit_rate_byte_1; 215 uint8_t bit_rate_byte_0; /* msb */ 216 uint8_t idle_cs_value_lsb; 217 uint8_t idle_cs_value_msb; 218 uint8_t active_cs_value_lsb; 219 uint8_t active_cs_value_msb; 220 uint8_t cs_to_data_delay_lsb; 221 uint8_t cs_to_data_delay_msb; 222 uint8_t lb_to_cs_deassert_delay_lsb; 223 uint8_t lb_to_cs_deassert_delay_msb; 224 uint8_t delay_between_bytes_lsb; 225 uint8_t delay_between_bytes_msb; 226 uint8_t bytes_per_spi_transaction_lsb; 227 uint8_t bytes_per_spi_transaction_msb; 228 uint8_t spi_mode; 229 uint8_t dontcare2[43]; 230 }; 231 232 struct mcp2210_get_spi_sram_req { 233 uint8_t cmd; /* MCP2210_CMD_GET_SPI_SRAM */ 234 uint8_t reserved[63]; 235 }; 236 237 #define MCP2210_SPI_MODE_0 0x00 238 #define MCP2210_SPI_MODE_1 0x01 239 #define MCP2210_SPI_MODE_2 0x02 240 #define MCP2210_SPI_MODE_3 0x03 241 242 struct mcp2210_get_spi_sram_res { 243 uint8_t cmd; 244 uint8_t completion; 245 uint8_t size_spi_res; 246 uint8_t dontcare; 247 uint8_t bit_rate_byte_3; /* lsb */ 248 uint8_t bit_rate_byte_2; 249 uint8_t bit_rate_byte_1; 250 uint8_t bit_rate_byte_0; /* msb */ 251 uint8_t idle_cs_value_lsb; 252 uint8_t idle_cs_value_msb; 253 uint8_t active_cs_value_lsb; 254 uint8_t active_cs_value_msb; 255 uint8_t cs_to_data_delay_lsb; 256 uint8_t cs_to_data_delay_msb; 257 uint8_t lb_to_cs_deassert_delay_lsb; 258 uint8_t lb_to_cs_deassert_delay_msb; 259 uint8_t delay_between_bytes_lsb; 260 uint8_t delay_between_bytes_msb; 261 uint8_t bytes_per_spi_transaction_lsb; 262 uint8_t bytes_per_spi_transaction_msb; 263 uint8_t spi_mode; 264 uint8_t dontcare2[43]; 265 }; 266 267 struct mcp2210_spi_transfer_req { 268 uint8_t cmd; /* MCP2210_CMD_SPI_TRANSFER */ 269 uint8_t num_send_bytes; 270 uint8_t reserved[2]; 271 uint8_t send_bytes[60]; 272 }; 273 274 #define MCP2210_SPI_STATUS_DATA_DONE 0x10 275 #define MCP2210_SPI_STATUS_NO_DATA_YET 0x20 276 #define MCP2210_SPI_STATUS_DATA 0x30 277 278 struct mcp2210_spi_transfer_res { 279 uint8_t cmd; 280 uint8_t completion; 281 uint8_t num_receive_bytes; 282 uint8_t spi_engine_status; 283 uint8_t receive_bytes[60]; 284 }; 285 286 struct mcp2210_set_gpio_value_req { 287 uint8_t cmd; /* MCP2210_CMD_SET_GPIO_VAL_SRAM */ 288 uint8_t reserved[3]; 289 uint8_t pin_value_lsb; 290 uint8_t pin_value_msb; 291 uint8_t reserved2[58]; 292 }; 293 294 struct mcp2210_set_gpio_value_res { 295 uint8_t cmd; 296 uint8_t completion; 297 uint8_t dontcare[2]; 298 uint8_t pin_value_lsb; 299 uint8_t pin_value_msb; 300 uint8_t dontcare2[58]; 301 }; 302 303 struct mcp2210_get_gpio_value_req { 304 uint8_t cmd; /* MCP2210_CMD_GET_GPIO_VAL_SRAM */ 305 uint8_t reserved[63]; 306 }; 307 308 struct mcp2210_get_gpio_value_res { 309 uint8_t cmd; 310 uint8_t completion; 311 uint8_t dontcare[2]; 312 uint8_t pin_value_lsb; 313 uint8_t pin_value_msb; 314 uint8_t dontcare2[58]; 315 }; 316 317 struct mcp2210_set_gpio_dir_req { 318 uint8_t cmd; /* MCP2210_CMD_SET_GPIO_DIR_SRAM */ 319 uint8_t reserved[3]; 320 uint8_t pin_dir_lsb; 321 uint8_t pin_dir_msb; 322 uint8_t reserved2[58]; 323 }; 324 325 struct mcp2210_set_gpio_dir_res { 326 uint8_t cmd; 327 uint8_t completion; 328 uint8_t dontcare[62]; 329 }; 330 331 332 struct mcp2210_get_gpio_dir_req { 333 uint8_t cmd; /* MCP2210_CMD_GET_GPIO_DIR_SRAM */ 334 uint8_t reserved[63]; 335 }; 336 337 struct mcp2210_get_gpio_dir_res { 338 uint8_t cmd; 339 uint8_t completion; 340 uint8_t dontcare[2]; 341 uint8_t pin_dir_lsb; 342 uint8_t pin_dir_msb; 343 uint8_t dontcare2[58]; 344 }; 345 346 struct mcp2210_read_eeprom_req { 347 uint8_t cmd; /* MCP2210_CMD_READ_EEPROM */ 348 uint8_t addr; 349 uint8_t dontcare[62]; 350 }; 351 352 struct mcp2210_read_eeprom_res { 353 uint8_t cmd; 354 uint8_t completion; 355 uint8_t addr; 356 uint8_t value; 357 uint8_t dontcare[60]; 358 }; 359 360 struct mcp2210_write_eeprom_req { 361 uint8_t cmd; /* MCP2210_CMD_WRITE_EEPROM */ 362 uint8_t addr; 363 uint8_t value; 364 uint8_t dontcare[61]; 365 }; 366 367 struct mcp2210_write_eeprom_res { 368 uint8_t cmd; 369 uint8_t completion; 370 uint8_t dontcare[62]; 371 }; 372 373 #define MCP2210_NVRAM_SUBCODE_SPI 0x10 374 #define MCP2210_NVRAM_SUBCODE_CS 0x20 375 #define MCP2210_NVRAM_SUBCODE_USBKEYPARAMS 0x30 376 #define MCP2210_NVRAM_SUBCODE_USBPROD 0x40 377 #define MCP2210_NVRAM_SUBCODE_USBMAN 0x50 378 379 #define MCP2210_USBPOWER_SELF 0x40 380 #define MCP2210_USBPOWER_BUSS 0x80 381 382 struct mcp2210_set_nvram_req { 383 uint8_t cmd; /* MCP2210_CMD_SET_NVRAM */ 384 uint8_t subcode; 385 uint8_t reserved[2]; 386 union { 387 struct { 388 uint8_t bit_rate_byte_3; /* lsb */ 389 uint8_t bit_rate_byte_2; 390 uint8_t bit_rate_byte_1; 391 uint8_t bit_rate_byte_0; /* msb */ 392 uint8_t idle_cs_value_lsb; 393 uint8_t idle_cs_value_msb; 394 uint8_t active_cs_value_lsb; 395 uint8_t active_cs_value_msb; 396 uint8_t cs_to_data_delay_lsb; 397 uint8_t cs_to_data_delay_msb; 398 uint8_t lb_to_cs_deassert_delay_lsb; 399 uint8_t lb_to_cs_deassert_delay_msb; 400 uint8_t delay_between_bytes_lsb; 401 uint8_t delay_between_bytes_msb; 402 uint8_t bytes_per_spi_transaction_lsb; 403 uint8_t bytes_per_spi_transaction_msb; 404 uint8_t spi_mode; 405 uint8_t dontcare[43]; 406 } spi; 407 struct { 408 uint8_t gp0_designation; 409 uint8_t gp1_designation; 410 uint8_t gp2_designation; 411 uint8_t gp3_designation; 412 uint8_t gp4_designation; 413 uint8_t gp5_designation; 414 uint8_t gp6_designation; 415 uint8_t gp7_designation; 416 uint8_t gp8_designation; 417 uint8_t default_output_lsb; 418 uint8_t default_output_msb; 419 uint8_t default_direction_lsb; 420 uint8_t default_direction_msb; 421 uint8_t other_settings; 422 uint8_t nvram_protection; 423 uint8_t password_byte_1; 424 uint8_t password_byte_2; 425 uint8_t password_byte_3; 426 uint8_t password_byte_4; 427 uint8_t password_byte_5; 428 uint8_t password_byte_6; 429 uint8_t password_byte_7; 430 uint8_t password_byte_8; 431 uint8_t dontcare[37]; 432 } cs; 433 struct { 434 uint8_t lsb_usb_vid; 435 uint8_t msb_usb_vid; 436 uint8_t lsb_usb_pid; 437 uint8_t msb_usb_pid; 438 uint8_t usb_power_attributes; 439 uint8_t usb_requested_ma; 440 uint8_t dontcare3[54]; 441 } usbkeyparams; 442 struct { 443 uint8_t total_length; 444 uint8_t always0x03; 445 uint8_t unicode_product_descriptor[58]; 446 } usbprod; 447 struct { 448 uint8_t total_length; 449 uint8_t always0x03; 450 uint8_t unicode_man_descriptor[58]; 451 } usbman; 452 } u; 453 }; 454 455 struct mcp2210_set_nvram_res { 456 uint8_t cmd; 457 uint8_t completion; 458 uint8_t subcode; 459 uint8_t dontcare[61]; 460 }; 461 462 struct mcp2210_get_nvram_req { 463 uint8_t cmd; /* MCP2210_CMD_GET_NVRAM */ 464 uint8_t subcode; 465 uint8_t reserved[62]; 466 }; 467 468 struct mcp2210_get_nvram_res { 469 uint8_t cmd; 470 uint8_t completion; 471 uint8_t subcode; 472 uint8_t dontcare; 473 union { 474 struct { 475 uint8_t bit_rate_byte_3; /* lsb */ 476 uint8_t bit_rate_byte_2; 477 uint8_t bit_rate_byte_1; 478 uint8_t bit_rate_byte_0; /* msb */ 479 uint8_t idle_cs_value_lsb; 480 uint8_t idle_cs_value_msb; 481 uint8_t active_cs_value_lsb; 482 uint8_t active_cs_value_msb; 483 uint8_t cs_to_data_delay_lsb; 484 uint8_t cs_to_data_delay_msb; 485 uint8_t lb_to_cs_deassert_delay_lsb; 486 uint8_t lb_to_cs_deassert_delay_msb; 487 uint8_t delay_between_bytes_lsb; 488 uint8_t delay_between_bytes_msb; 489 uint8_t bytes_per_spi_transaction_lsb; 490 uint8_t bytes_per_spi_transaction_msb; 491 uint8_t spi_mode; 492 uint8_t dontcare[43]; 493 } spi; 494 struct { 495 uint8_t gp0_designation; 496 uint8_t gp1_designation; 497 uint8_t gp2_designation; 498 uint8_t gp3_designation; 499 uint8_t gp4_designation; 500 uint8_t gp5_designation; 501 uint8_t gp6_designation; 502 uint8_t gp7_designation; 503 uint8_t gp8_designation; 504 uint8_t default_output_lsb; 505 uint8_t default_output_msb; 506 uint8_t default_direction_lsb; 507 uint8_t default_direction_msb; 508 uint8_t other_settings; 509 uint8_t nvram_protection; 510 uint8_t dontcare[45]; 511 } cs; 512 struct { 513 uint8_t dontcare[8]; 514 uint8_t lsb_usb_vid; 515 uint8_t msb_usb_vid; 516 uint8_t lsb_usb_pid; 517 uint8_t msb_usb_pid; 518 uint8_t dontcare2[13]; 519 uint8_t usb_power_attributes; 520 uint8_t usb_requested_ma; 521 uint8_t dontcare3[33]; 522 } usbkeyparams; 523 struct { 524 uint8_t total_length; 525 uint8_t always0x03; 526 uint8_t unicode_product_descriptor[58]; 527 } usbprod; 528 struct { 529 uint8_t total_length; 530 uint8_t always0x03; 531 uint8_t unicode_man_descriptor[58]; 532 } usbman; 533 } u; 534 }; 535 536 struct mcp2210_release_spi_bus_req { 537 uint8_t cmd; /* MCP2210_CMD_SPI_BUS_RELEASE */ 538 uint8_t reserved[63]; 539 }; 540 541 struct mcp2210_release_spi_bus_res { 542 uint8_t cmd; 543 uint8_t completion; 544 uint8_t dontcare[62]; 545 }; 546 547 /* MCP-2221 / MCP-2221A stuff */ 548 549 #define MCP2221_REQ_BUFFER_SIZE UMCPMIO_REQ_BUFFER_SIZE 550 #define MCP2221_RES_BUFFER_SIZE UMCPMIO_RES_BUFFER_SIZE 551 552 #define MCP2221_CMD_STATUS 0x10 553 554 #define MCP2221_CMD_I2C_FETCH_READ_DATA 0x40 555 556 #define MCP2221_CMD_SET_GPIO_CFG 0x50 557 #define MCP2221_CMD_GET_GPIO_CFG 0x51 558 559 #define MCP2221_CMD_SET_SRAM 0x60 560 #define MCP2221_CMD_GET_SRAM 0x61 561 562 #define MCP2221_I2C_WRITE_DATA 0x90 563 #define MCP2221_I2C_READ_DATA 0x91 564 #define MCP2221_I2C_WRITE_DATA_RS 0x92 565 #define MCP2221_I2C_READ_DATA_RS 0x93 566 #define MCP2221_I2C_WRITE_DATA_NS 0x94 567 568 #define MCP2221_CMD_GET_FLASH 0xb0 569 #define MCP2221_CMD_SET_FLASH 0xb1 570 #define MCP2221_CMD_SEND_FLASH_PASSWORD 0xb2 571 572 #define MCP2221_CMD_COMPLETE_OK 0x00 573 #define MCP2221_CMD_COMPLETE_NO_SUPPORT 0x02 574 #define MCP2221_CMD_COMPLETE_EPERM 0x03 575 576 #define MCP2221_I2C_DO_CANCEL 0x10 577 #define MCP2221_INTERNAL_CLOCK 12000000 578 #define MCP2221_DEFAULT_I2C_SPEED 100000 579 #define MCP2221_I2C_SET_SPEED 0x20 580 581 /* The request and response structures are, perhaps, over literal. */ 582 583 struct mcp2221_status_req { 584 uint8_t cmd; /* MCP2221_CMD_STATUS */ 585 uint8_t dontcare1; 586 uint8_t cancel_transfer; 587 uint8_t set_i2c_speed; 588 uint8_t i2c_clock_divider; 589 uint8_t dontcare2[59]; 590 }; 591 592 #define MCP2221_I2C_SPEED_SET 0x20 593 #define MCP2221_I2C_SPEED_BUSY 0x21 594 #define MCP2221_ENGINE_T1_MASK_NACK 0x40 595 596 struct mcp2221_status_res { 597 uint8_t cmd; 598 uint8_t completion; 599 uint8_t cancel_transfer; 600 uint8_t set_i2c_speed; 601 uint8_t i2c_clock_divider; 602 uint8_t dontcare2[3]; 603 uint8_t internal_i2c_state; 604 uint8_t lsb_i2c_req_len; 605 uint8_t msb_i2c_req_len; 606 uint8_t lsb_i2c_trans_len; 607 uint8_t msb_i2c_trans_len; 608 uint8_t internal_i2c_bcount; 609 uint8_t i2c_speed_divider; 610 uint8_t i2c_timeout_value; 611 uint8_t lsb_i2c_address; 612 uint8_t msb_i2c_address; 613 uint8_t dontcare3a[2]; 614 uint8_t internal_i2c_state20; 615 uint8_t dontcare3b; 616 uint8_t scl_line_value; 617 uint8_t sda_line_value; 618 uint8_t interrupt_edge_state; 619 uint8_t i2c_read_pending; 620 uint8_t dontcare4[20]; 621 uint8_t mcp2221_hardware_rev_major; 622 uint8_t mcp2221_hardware_rev_minor; 623 uint8_t mcp2221_firmware_rev_major; 624 uint8_t mcp2221_firmware_rev_minor; 625 uint8_t adc_channel0_lsb; 626 uint8_t adc_channel0_msb; 627 uint8_t adc_channel1_lsb; 628 uint8_t adc_channel1_msb; 629 uint8_t adc_channel2_lsb; 630 uint8_t adc_channel2_msb; 631 uint8_t dontcare5[8]; 632 }; 633 634 #define MCP2221_GPIO_CFG_ALTER 0xff 635 636 struct mcp2221_set_gpio_cfg_req { 637 uint8_t cmd; /* MCP2221_CMD_SET_GPIO_CFG */ 638 uint8_t dontcare1; 639 640 uint8_t alter_gp0_value; 641 uint8_t new_gp0_value; 642 uint8_t alter_gp0_dir; 643 uint8_t new_gp0_dir; 644 645 uint8_t alter_gp1_value; 646 uint8_t new_gp1_value; 647 uint8_t alter_gp1_dir; 648 uint8_t new_gp1_dir; 649 650 uint8_t alter_gp2_value; 651 uint8_t new_gp2_value; 652 uint8_t alter_gp2_dir; 653 uint8_t new_gp2_dir; 654 655 uint8_t alter_gp3_value; 656 uint8_t new_gp3_value; 657 uint8_t alter_gp3_dir; 658 uint8_t new_gp3_dir; 659 660 uint8_t reserved[46]; 661 }; 662 663 struct mcp2221_set_gpio_cfg_res { 664 uint8_t cmd; 665 uint8_t completion; 666 667 uint8_t alter_gp0_value; 668 uint8_t new_gp0_value; 669 uint8_t alter_gp0_dir; 670 uint8_t new_gp0_dir; 671 672 uint8_t alter_gp1_value; 673 uint8_t new_gp1_value; 674 uint8_t alter_gp1_dir; 675 uint8_t new_gp1_dir; 676 677 uint8_t alter_gp2_value; 678 uint8_t new_gp2_value; 679 uint8_t alter_gp2_dir; 680 uint8_t new_gp2_dir; 681 682 uint8_t alter_gp3_value; 683 uint8_t new_gp3_value; 684 uint8_t alter_gp3_dir; 685 uint8_t new_gp3_dir; 686 687 uint8_t dontcare[46]; 688 }; 689 690 struct mcp2221_get_gpio_cfg_req { 691 uint8_t cmd; /* MCP2221_CMD_GET_GPIO_CFG */ 692 uint8_t dontcare[63]; 693 }; 694 695 #define MCP2221_GPIO_CFG_VALUE_NOT_GPIO 0xEE 696 #define MCP2221_GPIO_CFG_DIR_NOT_GPIO 0xEF 697 #define MCP2221_GPIO_CFG_DIR_INPUT 0x01 698 #define MCP2221_GPIO_CFG_DIR_OUTPUT 0x00 699 700 struct mcp2221_get_gpio_cfg_res { 701 uint8_t cmd; 702 uint8_t completion; 703 704 uint8_t gp0_pin_value; 705 uint8_t gp0_pin_dir; 706 707 uint8_t gp1_pin_value; 708 uint8_t gp1_pin_dir; 709 710 uint8_t gp2_pin_value; 711 uint8_t gp2_pin_dir; 712 713 uint8_t gp3_pin_value; 714 uint8_t gp3_pin_dir; 715 716 uint8_t dontcare[54]; 717 }; 718 719 #define MCP2221_SRAM_GPIO_CHANGE_DCCD 0x80 720 721 #define MCP2221_SRAM_GPIO_CLOCK_DC_MASK 0x18 722 #define MCP2221_SRAM_GPIO_CLOCK_DC_75 0x18 723 #define MCP2221_SRAM_GPIO_CLOCK_DC_50 0x10 724 #define MCP2221_SRAM_GPIO_CLOCK_DC_25 0x08 725 #define MCP2221_SRAM_GPIO_CLOCK_DC_0 0x00 726 727 #define MCP2221_SRAM_GPIO_CLOCK_CD_MASK 0x07 728 #define MCP2221_SRAM_GPIO_CLOCK_CD_375KHZ 0x07 729 #define MCP2221_SRAM_GPIO_CLOCK_CD_750KHZ 0x06 730 #define MCP2221_SRAM_GPIO_CLOCK_CD_1P5MHZ 0x05 731 #define MCP2221_SRAM_GPIO_CLOCK_CD_3MHZ 0x04 732 #define MCP2221_SRAM_GPIO_CLOCK_CD_6MHZ 0x03 733 #define MCP2221_SRAM_GPIO_CLOCK_CD_12MHZ 0x02 734 #define MCP2221_SRAM_GPIO_CLOCK_CD_24MHZ 0x01 735 736 #define MCP2221_SRAM_CHANGE_DAC_VREF 0x80 737 #define MCP2221_SRAM_DAC_IS_VRM 0x20 738 #define MCP2221_SRAM_DAC_VRM_MASK 0xC0 739 #define MCP2221_SRAM_DAC_VRM_4096V 0xC0 740 #define MCP2221_SRAM_DAC_VRM_2048V 0x80 741 #define MCP2221_SRAM_DAC_VRM_1024V 0x40 742 #define MCP2221_SRAM_DAC_VRM_OFF 0x00 743 #define MCP2221_SRAM_CHANGE_DAC_VALUE 0x80 744 #define MCP2221_SRAM_DAC_VALUE_MASK 0x1F 745 746 #define MCP2221_SRAM_CHANGE_ADC_VREF 0x80 747 #define MCP2221_SRAM_ADC_IS_VRM 0x04 748 #define MCP2221_SRAM_ADC_VRM_MASK 0x18 749 #define MCP2221_SRAM_ADC_VRM_4096V 0x18 750 #define MCP2221_SRAM_ADC_VRM_2048V 0x10 751 #define MCP2221_SRAM_ADC_VRM_1024V 0x08 752 #define MCP2221_SRAM_ADC_VRM_OFF 0x00 753 754 #define MCP2221_SRAM_ALTER_IRQ 0x80 755 #define MCP2221_SRAM_ALTER_POS_EDGE 0x10 756 #define MCP2221_SRAM_ENABLE_POS_EDGE 0x08 757 #define MCP2221_SRAM_ALTER_NEG_EDGE 0x04 758 #define MCP2221_SRAM_ENABLE_NEG_EDGE 0x02 759 #define MCP2221_SRAM_CLEAR_IRQ 0x01 760 761 #define MCP2221_SRAM_ALTER_GPIO 0xff 762 #define MCP2221_SRAM_GPIO_HIGH 0x0f 763 #define MCP2221_SRAM_GPIO_OUTPUT_HIGH 0x10 764 #define MCP2221_SRAM_GPIO_TYPE_MASK 0x08 765 #define MCP2221_SRAM_GPIO_INPUT 0x08 766 #define MCP2221_SRAM_PIN_TYPE_MASK 0x07 767 #define MCP2221_SRAM_PIN_IS_GPIO 0x00 768 #define MCP2221_SRAM_PIN_IS_DED 0x01 769 #define MCP2221_SRAM_PIN_IS_ALT0 0x02 770 #define MCP2221_SRAM_PIN_IS_ALT1 0x03 771 #define MCP2221_SRAM_PIN_IS_ALT2 0x04 772 773 struct mcp2221_set_sram_req { 774 uint8_t cmd; /* MCP2221_CMD_SET_SRAM */ 775 uint8_t dontcare1; 776 777 uint8_t clock_output_divider; 778 uint8_t dac_voltage_reference; 779 uint8_t set_dac_output_value; 780 uint8_t adc_voltage_reference; 781 uint8_t irq_config; 782 783 uint8_t alter_gpio_config; 784 uint8_t gp0_settings; 785 uint8_t gp1_settings; 786 uint8_t gp2_settings; 787 uint8_t gp3_settings; 788 789 uint8_t reserved[52]; 790 }; 791 792 struct mcp2221_set_sram_res { 793 uint8_t cmd; 794 uint8_t completion; 795 uint8_t dontcare[62]; 796 }; 797 798 struct mcp2221_get_sram_req { 799 uint8_t cmd; /* MCP2221_CMD_GET_SRAM */ 800 uint8_t dontcare[63]; 801 }; 802 803 struct mcp2221_get_sram_res { 804 uint8_t cmd; 805 uint8_t completion; 806 807 uint8_t len_chip_setting; 808 uint8_t len_gpio_setting; 809 810 uint8_t sn_initial_ps_cs; 811 uint8_t clock_divider; 812 uint8_t dac_reference_voltage; 813 uint8_t irq_adc_reference_voltage; 814 815 uint8_t lsb_usb_vid; 816 uint8_t msb_usb_vid; 817 uint8_t lsb_usb_pid; 818 uint8_t msb_usb_pid; 819 820 uint8_t usb_power_attributes; 821 uint8_t usb_requested_ma; 822 823 uint8_t current_password_byte_1; 824 uint8_t current_password_byte_2; 825 uint8_t current_password_byte_3; 826 uint8_t current_password_byte_4; 827 uint8_t current_password_byte_5; 828 uint8_t current_password_byte_6; 829 uint8_t current_password_byte_7; 830 uint8_t current_password_byte_8; 831 832 uint8_t gp0_settings; 833 uint8_t gp1_settings; 834 uint8_t gp2_settings; 835 uint8_t gp3_settings; 836 837 uint8_t dontcare[38]; 838 }; 839 840 #define MCP2221_I2C_ENGINE_BUSY 0x01 841 #define MCP2221_ENGINE_STARTTIMEOUT 0x12 842 #define MCP2221_ENGINE_REPSTARTTIMEOUT 0x17 843 #define MCP2221_ENGINE_STOPTIMEOUT 0x62 844 #define MCP2221_ENGINE_ADDRSEND 0x21 845 #define MCP2221_ENGINE_ADDRTIMEOUT 0x23 846 #define MCP2221_ENGINE_PARTIALDATA 0x41 847 #define MCP2221_ENGINE_READMORE 0x43 848 #define MCP2221_ENGINE_WRITETIMEOUT 0x44 849 #define MCP2221_ENGINE_READTIMEOUT 0x52 850 #define MCP2221_ENGINE_READPARTIAL 0x54 851 #define MCP2221_ENGINE_READCOMPLETE 0x55 852 #define MCP2221_ENGINE_ADDRNACK 0x25 853 #define MCP2221_ENGINE_WRITINGNOSTOP 0x45 854 855 struct mcp2221_i2c_req { 856 uint8_t cmd; /* MCP2221_I2C_WRITE_DATA 857 * MCP2221_I2C_READ_DATA 858 * MCP2221_I2C_WRITE_DATA_RS 859 * MCP2221_I2C_READ_DATA_RS 860 * MCP2221_I2C_WRITE_DATA_NS 861 */ 862 uint8_t lsblen; 863 uint8_t msblen; 864 uint8_t slaveaddr; 865 uint8_t data[60]; 866 }; 867 868 struct mcp2221_i2c_res { 869 uint8_t cmd; 870 uint8_t completion; 871 uint8_t internal_i2c_state; 872 uint8_t dontcare[61]; 873 }; 874 875 #define MCP2221_FETCH_READ_PARTIALDATA 0x41 876 #define MCP2221_FETCH_READERROR 0x7F 877 878 struct mcp2221_i2c_fetch_req { 879 uint8_t cmd; /* MCP2221_CMD_I2C_FETCH_READ_DATA */ 880 uint8_t dontcare[63]; 881 }; 882 883 struct mcp2221_i2c_fetch_res { 884 uint8_t cmd; 885 uint8_t completion; 886 uint8_t internal_i2c_state; 887 uint8_t fetchlen; 888 uint8_t data[60]; 889 }; 890 891 #define MCP2221_FLASH_SUBCODE_CS 0x00 892 #define MCP2221_FLASH_SUBCODE_GP 0x01 893 #define MCP2221_FLASH_SUBCODE_USBMAN 0x02 894 #define MCP2221_FLASH_SUBCODE_USBPROD 0x03 895 #define MCP2221_FLASH_SUBCODE_USBSN 0x04 896 #define MCP2221_FLASH_SUBCODE_CHIPSN 0x05 897 898 struct mcp2221_get_flash_req { 899 uint8_t cmd; /* MCP2221_CMD_GET_FLASH */ 900 uint8_t subcode; 901 uint8_t reserved[62]; 902 }; 903 904 struct mcp2221_get_flash_res { 905 uint8_t cmd; 906 uint8_t completion; 907 uint8_t res_len; 908 union { 909 struct { 910 uint8_t dontcare; 911 uint8_t uartenum_led_protection; 912 uint8_t clock_divider; 913 uint8_t dac_reference_voltage; 914 uint8_t irq_adc_reference_voltage; 915 uint8_t lsb_usb_vid; 916 uint8_t msb_usb_vid; 917 uint8_t lsb_usb_pid; 918 uint8_t msb_usb_pid; 919 uint8_t usb_power_attributes; 920 uint8_t usb_requested_ma; 921 uint8_t dontcare2[50]; 922 } cs; 923 struct { 924 uint8_t dontcare; 925 uint8_t gp0_settings; 926 uint8_t gp1_settings; 927 uint8_t gp2_settings; 928 uint8_t gp3_settings; 929 uint8_t dontcare2[56]; 930 } gp; 931 struct { 932 uint8_t always0x03; 933 uint8_t unicode_man_descriptor[60]; 934 } usbman; 935 struct { 936 uint8_t always0x03; 937 uint8_t unicode_product_descriptor[60]; 938 } usbprod; 939 struct usbsn { 940 uint8_t always0x03; 941 uint8_t unicode_serial_number[60]; 942 } usbsn; 943 struct { 944 uint8_t dontcare; 945 uint8_t factory_serial_number[60]; 946 } chipsn; 947 } u; 948 }; 949 950 #define MCP2221_FLASH_GPIO_HIGH 0x0f 951 #define MCP2221_FLASH_GPIO_VALUE_MASK 0x10 952 #define MCP2221_FLASH_GPIO_TYPE_MASK 0x08 953 #define MCP2221_FLASH_GPIO_INPUT 0x08 954 #define MCP2221_FLASH_PIN_TYPE_MASK 0x07 955 #define MCP2221_FLASH_PIN_IS_GPIO 0x00 956 #define MCP2221_FLASH_PIN_IS_DED 0x01 957 #define MCP2221_FLASH_PIN_IS_ALT0 0x02 958 #define MCP2221_FLASH_PIN_IS_ALT1 0x03 959 #define MCP2221_FLASH_PIN_IS_ALT2 0x04 960 961 struct mcp2221_put_flash_req { 962 uint8_t cmd; /* MCP2221_CMD_SET_FLASH */ 963 uint8_t subcode; 964 union { 965 struct { 966 uint8_t uartenum_led_protection; 967 uint8_t clock_divider; 968 uint8_t dac_reference_voltage; 969 uint8_t irq_adc_reference_voltage; 970 uint8_t lsb_usb_vid; 971 uint8_t msb_usb_vid; 972 uint8_t lsb_usb_pid; 973 uint8_t msb_usb_pid; 974 uint8_t usb_power_attributes; 975 uint8_t usb_requested_ma; 976 uint8_t password_byte_1; 977 uint8_t password_byte_2; 978 uint8_t password_byte_3; 979 uint8_t password_byte_4; 980 uint8_t password_byte_5; 981 uint8_t password_byte_6; 982 uint8_t password_byte_7; 983 uint8_t password_byte_8; 984 uint8_t dontcare[44]; 985 } cs; 986 struct { 987 uint8_t gp0_settings; 988 uint8_t gp1_settings; 989 uint8_t gp2_settings; 990 uint8_t gp3_settings; 991 uint8_t dontcare[58]; 992 } gp; 993 struct { 994 uint8_t len; 995 uint8_t always0x03; 996 uint8_t unicode_man_descriptor[60]; 997 } usbman; 998 struct { 999 uint8_t len; 1000 uint8_t always0x03; 1001 uint8_t unicode_product_descriptor[60]; 1002 } usbprod; 1003 struct { 1004 uint8_t len; 1005 uint8_t always0x03; 1006 uint8_t unicode_serial_number[60]; 1007 } usbsn; 1008 } u; 1009 }; 1010 1011 struct mcp2221_put_flash_res { 1012 uint8_t cmd; 1013 uint8_t completion; 1014 uint8_t dontcare[62]; 1015 }; 1016 1017 /* XXX - missing is the submit password call to unlock the chip */ 1018 1019 #endif /* _UMCPMIO_HID_REPORTS_H_ */ 1020
Indexes created Sat Feb 21 16:20:20 UTC 2026