| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_r600_cs.c | 245 int array_mode; member in struct:array_mode_checker
267 switch (values->array_mode) {
363 unsigned array_mode; local
382 array_mode = G_0280A0_ARRAY_MODE(track->cb_color_info[i]);
385 array_check.array_mode = array_mode;
398 switch (array_mode) {
419 __func__, __LINE__, pitch, pitch_align, array_mode);
424 __func__, __LINE__, height, height_align, array_mode);
429 base_offset, base_align, array_mode);
530 int array_mode; local
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| amdgpu_dc_debug.c | 160 "plane_state->tiling_info.gfx8.array_mode = %d;\n"
167 plane_state->tiling_info.gfx8.array_mode,
252 "plane_info->tiling_info.gfx8.array_mode = %d;\n"
256 update->plane_info->tiling_info.gfx8.array_mode,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| amdgpu_dce_mem_input.c | 108 switch (tiling_info->gfx8.array_mode) {
386 GRPH_ARRAY_MODE, info->gfx8.array_mode,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| dc_hw_types.h | 343 enum array_mode_values array_mode; member in struct:dc_tiling_info::__anon4574
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| amdgpu_dce110_mem_input_v.c | 198 set_reg_field_value(value, info->gfx8.array_mode,
550 switch (tiling_info->gfx8.array_mode) {
|
| amdgpu_dce110_hw_sequencer.c | 1837 if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/ |
| amdgpu_dm.c | 3262 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
3273 tiling_info->gfx8.array_mode =
3281 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
3283 tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
|
