| /src/sys/arch/riscv/riscv/ |
| riscv_tlb.c | 55 tlb_set_asid(tlb_asid_t asid, struct pmap *pm)
57 csr_asid_write(asid);
78 tlb_asid_t asid; local in function:tlb_invalidate_asids
79 for (asid = lo; asid <= hi; asid++) {
80 asm volatile("sfence.vma zero, %[asid]"
82 : [asid] "r" (asid)
100 for (asid = lo; asid <= hi; asid++)
[all...] |
| sbi.c | 123 unsigned long size, unsigned long asid)
126 hart_mask, hart_mask_base, start_addr, size, asid);
150 unsigned long size, unsigned long asid)
153 hart_mask, hart_mask_base, start_addr, size, asid);
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| trap.c | 443 tlb_asid_t asid = tlb_get_asid(); local in function:trap_pagefault
450 asid, ptep, ptep ? pte_value(*ptep) : 0);
|
| /src/sys/arch/aarch64/aarch64/ |
| aarch64_tlb.c | 53 tlb_set_asid(tlb_asid_t asid, pmap_t pm)
56 __SHIFTIN(asid, TTBR_ASID) |
84 tlb_invalidate_addr(vaddr_t va, tlb_asid_t asid)
88 aarch64_tlbi_by_asid_va(asid, va);
92 tlb_update_addr(vaddr_t va, tlb_asid_t asid, pt_entry_t pte, bool insert_p)
96 tlb_invalidate_addr(va, asid);
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| pmap.c | 164 * invalidate TLB entry for ASID and VA.
166 #define AARCH64_TLBI_BY_ASID_VA(asid, va) \
168 if ((asid) == 0) \
171 aarch64_tlbi_by_asid_va((asid), (va)); \
179 #define PTE_ICACHE_SYNC_PAGE(pte, ptep, asid, va) \
182 AARCH64_TLBI_BY_ASID_VA((asid), (va)); \
1140 pr(" pv[%d].pv_pmap = %p (asid=%d)\n", i, pm, pai->pai_asid);
1404 UVMHIST_LOG(pmaphist, "setting asid to %#jx", pai->pai_asid,
1441 UVMHIST_LOG(pmaphist, "lwp=%p, asid=%d", l,
1470 UVMHIST_LOG(pmaphist, "setting asid to %#jx", KERNEL_PID
2030 const tlb_asid_t asid = pai->pai_asid; local in function:_pmap_enter
[all...] |
| /src/sys/arch/arm/arm32/ |
| arm32_tlb.c | 53 tlb_set_asid(tlb_asid_t asid, pmap_t pm)
56 if (asid == KERNEL_PID) {
60 armreg_contextidr_write(asid);
125 tlb_invalidate_addr(vaddr_t va, tlb_asid_t asid)
128 va = trunc_page(va) | asid;
140 tlb_update_addr(vaddr_t va, tlb_asid_t asid, pt_entry_t pte, bool insert_p)
142 tlb_invalidate_addr(va, asid);
163 const tlb_asid_t asid = __SHIFTOUT(d, local in function:tlb_cortex_a5_record_asids
165 const u_long mask = 1L << (asid & 31);
166 const size_t idx = asid >> 5
196 const tlb_asid_t asid = __SHIFTOUT(d01, local in function:tlb_cortex_a7_record_asids
[all...] |
| db_machdep.c | 244 tlb_print_asid(bool ng_p, tlb_asid_t asid)
247 db_printf(" %3d", asid);
298 const tlb_asid_t asid = __SHIFTOUT(d, ARM_A5_TLBDATA_ASID); local in function:tlb_print_cortex_a5_entry
300 tlb_print_asid(ng_p, asid);
361 const tlb_asid_t asid = __SHIFTOUT(d01, ARM_A7_TLBDATA01_ASID); local in function:tlb_print_cortex_a7_entry
363 tlb_print_asid(ng_p, asid);
|
| /src/sys/arch/sh3/sh3/ |
| mmu_sh3.c | 49 /* Set current ASID to 0 - kernel */
77 sh3_tlb_invalidate_asid(int asid)
88 if ((_reg_read_4(aa) & SH3_MMUAA_D_ASID_MASK) == asid)
96 sh3_tlb_invalidate_addr(int asid, vaddr_t va)
102 match = (va & SH3_MMUAA_D_VPN_MASK_4K) | asid;
123 sh3_tlb_update(int asid, vaddr_t va, uint32_t pte)
133 KDASSERT(asid < 256 && (pte & ~PGOFSET) != 0 && va != 0);
137 sh3_tlb_invalidate_addr(asid, va);
156 match = (va & SH3_MMUAA_D_VPN_MASK_4K) | asid;
|
| mmu_sh4.c | 58 /* Set current ASID to 0 */
75 * address. Note, the ASID match is against PTEH, not "va". The
88 sh4_tlb_invalidate_addr(int asid, vaddr_t va)
99 opteh = _reg_read_4(SH4_PTEH); /* save current ASID */
101 _reg_write_4(SH4_PTEH, asid); /* set ASID for associative write */
102 (*tlb_assoc_p2)(va); /* invalidate { va, ASID } entry if exists */
104 _reg_write_4(SH4_PTEH, opteh); /* restore ASID */
110 do_invalidate_asid(int asid)
117 if ((aa & SH4_UTLB_AA_ASID_MASK) == asid)
[all...] |
| mmu.c | 86 r & SH3_MMUCR_IX ? "ASID+VPN" : "VPN",
108 sh_tlb_set_asid(int asid)
111 _reg_write_4(SH_(PTEH), asid);
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| pmap.c | 89 /* ASID ops. */
286 /* Free ASID */
536 * When pmap->pm_asid == -1 (invalid ASID), old entry attribute
1056 /* When pmap has valid ASID, register to TLB */
1065 * Allocate new ASID. if all ASID is used, steal from other process.
1071 int i, j, k, n, map, asid; local in function:__pmap_asid_alloc
1073 /* Search free ASID */
1088 /* Steal ASID */
1090 if ((asid = p->p_vmspace->vm_map.pmap->pm_asid) > 0)
[all...] |
| db_interface.c | 274 " VPN ASID PFN AREA VDCGWtPR SZ";
285 ? "ASID + VPN" : "VPN only",
288 db_printf("ASID=%d (%s)", i, __db_procname_by_asid(i));
305 int asid; local in function:db_tlbdump_cmd
306 asid = r & SH3_MMUAA_D_ASID_MASK;
310 (int)va < 0 ? 'K' : 'U', asid);
346 db_printf("ASID=%d (%s)", i, __db_procname_by_asid(i));
436 __db_procname_by_asid(int asid)
442 if (p->p_vmspace->vm_map.pmap->pm_asid == asid)
|
| /src/sys/arch/powerpc/booke/ |
| booke_stubs.c | 51 tlb_set_asid(tlb_asid_t asid, struct pmap *pm)
53 (*cpu_md_ops.md_tlb_ops->md_tlb_set_asid)(asid);
91 tlb_invalidate_addr(vaddr_t va, tlb_asid_t asid)
93 (*cpu_md_ops.md_tlb_ops->md_tlb_invalidate_addr)(va, asid);
99 tlb_update_addr(vaddr_t va, tlb_asid_t asid, pt_entry_t pte, bool insert_p)
101 return (*cpu_md_ops.md_tlb_ops->md_tlb_update_addr)(va, asid, pte, insert_p);
|
| e500_tlb.c | 241 * A non-zero ASID means this is a user page so mark it as
353 e500_tlb_set_asid(tlb_asid_t asid)
355 mtspr(SPR_PID0, asid);
450 * its asid matches the constraints of the caller,
488 * its asid matches the constraints of the caller,
492 const uint32_t asid = MASX_TID_GET(mas1); local in function:e500_tlb_record_asids
493 const u_int i = asid / nbits;
494 const u_long mask = 1UL << (asid & (nbits - 1));
508 e500_tlb_invalidate_addr(vaddr_t va, tlb_asid_t asid)
514 if (asid == KERNEL_PID)
[all...] |
| booke_pmap.c | 410 pmap_md_tlb_check_entry(void *ctx, vaddr_t va, tlb_asid_t asid, pt_entry_t pte)
415 if (asid != pai->pai_asid)
425 "pm=%p va=%#"PRIxVADDR" asid=%u: TLB pte (%#x) != real pte (%#x/%#x)",
426 pm, va, asid, pte, xpte, *ptep);
|
| /src/sys/uvm/pmap/ |
| pmap_tlb.c | 46 * that have a valid ASID.
49 * then reinitialize the ASID space, and start allocating again at 1. When
50 * allocating from the ASID bitmap, we skip any ASID who has a corresponding
51 * bit set in the ASID bitmap. Eventually this causes the ASID bitmap to fill
52 * and, when completely filled, a reinitialization of the ASID space.
54 * To reinitialize the ASID space, the ASID bitmap is reset and then the ASIDs
55 * of non-kernel TLB entries get recorded in the ASID bitmap. If the entrie
425 for (tlb_asid_t asid = 1; asid <= ti->ti_asid_max; asid++) { local in function:pmap_tlb_asid_count
[all...] |
| /src/sys/arch/riscv/include/ |
| sbi.h | 132 unsigned long asid);
146 unsigned long asid);
243 #define SBI_PMU_FW_SFENCE_VMA_ASID_SENT 12 // Sent SFENCE.VMA with ASID
245 #define SBI_PMU_FW_SFENCE_VMA_ASID_RECEIVED 13 // Received SFENCE.VMA with ASID
259 #define SBI_PMU_FW_HFENCE_VVMA_ASID_SENT 20 // Sent HFENCE.VVMA with ASID
261 #define SBI_PMU_FW_HFENCE_VVMA_ASID_RECEIVED 21 // Received HFENCE.VVMA with ASID
439 * unsigned long asid)
443 unsigned long start, unsigned long size, unsigned long asid)
446 (unsigned long)hart_mask, start, size, asid);
|
| sysreg.h | 325 /* Fake "ASID" CSR (a field of SATP register) functions */
334 csr_asid_write(uint32_t asid)
338 satp |= __SHIFTIN(asid, SATP_ASID);
|
| pmap.h | 187 pmap_md_tlb_check_entry(void *ctx, vaddr_t va, tlb_asid_t asid, pt_entry_t pte)
|
| /src/sys/arch/hpc/stand/hpcboot/sh3/ |
| sh_mmu.cpp | 46 uint32_t vpn, idx, s, dum, aae, dae, entry_idx, asid; local in function:MemoryManager_SHMMU::searchPage
55 // Get current ASID
56 asid = _reg_read_4(SH3_PTEH) & SH3_PTEH_ASID_MASK;
72 ((aae & SH3_MMUAA_D_ASID_MASK) != asid) ||
168 ? TEXT("ASID + VPN") : TEXT("VPN only"),
173 DPRINTF((TEXT(" VPN ASID PFN VDCG PR SZ\n")));
|
| /src/sys/arch/mips/mips/ |
| mips_fixup.c | 582 tlb_set_asid(uint32_t asid, struct pmap *pm)
584 (*mips_locore_jumpvec.ljv_tlb_set_asid)(asid);
594 tlb_invalidate_addr(vaddr_t va, tlb_asid_t asid)
596 (*mips_locore_jumpvec.ljv_tlb_invalidate_addr)(va, asid);
619 tlb_update_addr(vaddr_t va, tlb_asid_t asid, pt_entry_t pte, bool insert)
621 return (*mips_locore_jumpvec.ljv_tlb_update_addr)(va, asid, pte, insert);
|
| pmap_machdep.c | 854 pmap_md_tlb_check_entry(void *ctx, vaddr_t va, tlb_asid_t asid, pt_entry_t pte)
860 if (asid != pai->pai_asid)
870 KASSERTMSG(ptep != NULL, "va %#"PRIxVADDR" asid %u pte %#"PRIxPTE,
871 va, asid, pte_value(pte));
893 "pmap=%p va=%#"PRIxVADDR" asid=%u: TLB pte (%#"PRIxPTE
895 pm, va, asid, pte_value(pte), pte_value(xpte), pte_value(opte),
907 tlb_asid_t asid; local in function:tlb_walk
911 asid = __SHIFTOUT(tlbmask.tlb_hi, MIPS3_PG_ASID);
914 asid = __SHIFTOUT(tlbmask.tlb_hi, MIPS1_TLB_PID);
919 tlb_asid_t asid0 = (pte_global_p(pte) ? KERNEL_PID : asid);
[all...] |
| db_interface.c | 640 uint32_t asid; local in function:db_watch_cmd
647 "#", "MODE", "ADDR", "MASK", "ASID");
717 * if asid mode is requested, get the asid;
718 * otherwise use global mode (and set asid=0)
722 db_printf("asid missing\n");
726 asid = (uint32_t)(value & __BITS(7,0));
728 asid = 0;
742 cwp->cw_asid = asid;
919 "address <mask> <asid> </rwxma>", NULL) }
[all...] |
| /src/sys/arch/mips/rmi/ |
| rmixl_firmware.h | 140 int asid; member in struct:lib_cpu_tlb_mapping
|
| /src/sys/arch/aarch64/include/ |
| pmap_machdep.h | 177 pmap_md_tlb_check_entry(void *ctx, vaddr_t va, tlb_asid_t asid, pt_entry_t pte)
|
