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  /src/sys/arch/arm/dts/
rk3399-crypto.dtsi 36 assigned-clocks = <&cru SCLK_CRYPTO1>, <&cru HCLK_S_CRYPTO1>;
37 assigned-clock-rates = <150000000>, <100000000>;
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
omap443x.dtsi 84 assigned-clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 24>,
86 assigned-clock-rates = <0>, <307200000>;
87 assigned-clock-parents = <&dpll_per_m7x2_ck>;
bcm911360_entphn.dts 74 assigned-clocks =
77 assigned-clock-rates = <525000000>, <300000000>;
imx6ull-colibri-wifi.dtsi 41 assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>;
42 assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
43 assigned-clock-rates = <0>, <198000000>;
imx7d-remarkable2.dts 48 assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
50 assigned-clock-parents = <&clks IMX7D_CKIL>;
51 assigned-clock-rates = <0>, <32768>;
61 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
62 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
69 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
70 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
107 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
108 assigned-clock-rates = <400000000>;
imx7d-cl-som-imx7.dts 47 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
49 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
50 assigned-clock-rates = <0>, <100000000>;
75 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
77 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
78 assigned-clock-rates = <0>, <100000000>;
197 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
198 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
212 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
213 assigned-clock-rates = <400000000>
    [all...]
exynos5422-odroidxu3-audio.dtsi 56 assigned-clocks = <&clock CLK_MOUT_EPLL>,
66 assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
73 assigned-clock-rates = <0>,
exynos5422-odroidxu4.dts 51 assigned-clocks = <&clock CLK_MOUT_EPLL>,
61 assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
68 assigned-clock-rates = <0>,
omap2420-n810.dts 64 assigned-clocks = <&sys_clkout2_src>, <&sys_clkout2>;
65 assigned-clock-parents = <&func_96m_ck>;
66 assigned-clock-rates = <0>, <12000000>;
imx7ulp.dtsi 154 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
155 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
156 assigned-clock-rates = <24000000>;
166 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
167 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
168 assigned-clock-rates = <48000000>;
175 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
176 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
261 assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
262 assigned-clocks-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>
    [all...]
stih407.dtsi 16 assigned-clocks = <&clk_s_d2_quadfs 0>,
28 assigned-clock-parents = <0>,
40 assigned-clock-rates = <297000000>,
88 assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
95 assigned-clock-parents = <&clk_s_d2_quadfs 0>,
exynos4412-odroid-common.dtsi 126 assigned-clocks = <&clock CLK_FOUT_EPLL>;
127 assigned-clock-rates = <45158401>;
131 assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
137 assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
140 assigned-clock-rates = <0>, <0>,
208 assigned-clocks = <&clock CLK_MOUT_FIMC0>,
210 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
211 assigned-clock-rates = <0>, <176000000>;
216 assigned-clocks = <&clock CLK_MOUT_FIMC1>,
218 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>
    [all...]
imx7d-pico.dtsi 105 assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
107 assigned-clock-parents = <&clks IMX7D_CKIL>;
108 assigned-clock-rates = <0>, <32768>;
121 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
123 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
124 assigned-clock-rates = <0>, <100000000>;
278 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
280 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
281 assigned-clock-rates = <0>, <24576000>;
313 assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>
    [all...]
imx7s-warp.dts 84 assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
85 assigned-clock-rates = <884736000>;
268 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
270 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
271 assigned-clock-rates = <0>, <36864000>;
278 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
279 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
286 assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
287 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
295 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>
    [all...]
imx7d-zii-rpu2.dts 189 assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
190 assigned-clock-rates = <884736000>;
211 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
213 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
214 assigned-clock-rates = <0>, <100000000>;
294 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
296 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
297 assigned-clock-rates = <0>, <100000000>;
457 assigned-clocks = <&cs2000>;
458 assigned-clock-rates = <24000000>
    [all...]
am3517.dtsi 184 assigned-clocks = <&gpt1_fck>;
185 assigned-clock-parents = <&sys_ck>;
194 assigned-clocks = <&gpt2_fck>;
195 assigned-clock-parents = <&sys_ck>;
at91sam9g25ek.dts 27 assigned-clocks = <&pmc PMC_TYPE_SYSTEM 8>;
28 assigned-clock-rates = <25000000>;
exynos4412-itop-elite.dts 130 assigned-clocks = <&clock CLK_MOUT_CAM0>;
131 assigned-clock-parents = <&clock CLK_XUSBXTI>;
135 assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
139 assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
141 assigned-clock-rates = <0>, <0>, <112896000>, <11289600>;
159 assigned-clocks = <&clock CLK_MOUT_FIMC0>,
161 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
162 assigned-clock-rates = <0>, <176000000>;
imx7d-meerkat96.dts 143 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
144 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
151 assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
152 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
160 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
161 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
168 assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>;
169 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
imx7ulp-com.dts 40 assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
41 assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>;
rk3228-evb.dts 40 assigned-clocks = <&cru SCLK_MAC_SRC>;
41 assigned-clock-rates = <50000000>;
  /src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/starfive/
jh7110-pine64-star64.dts 19 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
20 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
27 assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
28 assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/freescale/
imx8-ss-img.dtsi 28 assigned-clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
30 assigned-clock-rates = <200000000>, <200000000>;
47 assigned-clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>,
49 assigned-clock-rates = <200000000>, <200000000>;
  /src/usr.bin/make/unit-tests/
var-scope-global.mk 5 # Global variables can be assigned and appended to.
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/ti/
k3-j721e-common-proc-board.dts 513 assigned-clocks = <&k3_clks 157 371>;
514 assigned-clock-parents = <&k3_clks 157 400>;
515 assigned-clock-rates = <24576000>; /* for 48KHz */
567 assigned-clocks = <&k3_clks 152 1>,
571 assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */
644 assigned-clocks = <&wiz0_pll1_refclk>;
645 assigned-clock-parents = <&cmn_refclk1>;
649 assigned-clocks = <&wiz0_refclk_dig>;
650 assigned-clock-parents = <&cmn_refclk1>;
654 assigned-clocks = <&wiz1_pll1_refclk>
    [all...]

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1 2 3 4 5 6 7 8 91011>>