1 /* $NetBSD: athn.c,v 1.26 2022/03/18 23:32:24 riastradh Exp $ */ 2 /* $OpenBSD: athn.c,v 1.83 2014/07/22 13:12:11 mpi Exp $ */ 3 4 /*- 5 * Copyright (c) 2009 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2008-2010 Atheros Communications Inc. 7 * 8 * Permission to use, copy, modify, and/or distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for Atheros 802.11a/g/n chipsets. 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: athn.c,v 1.26 2022/03/18 23:32:24 riastradh Exp $"); 27 28 #ifndef _MODULE 29 #include "athn_usb.h" /* for NATHN_USB */ 30 #endif 31 32 #include <sys/param.h> 33 #include <sys/sockio.h> 34 #include <sys/mbuf.h> 35 #include <sys/kernel.h> 36 #include <sys/socket.h> 37 #include <sys/systm.h> 38 #include <sys/malloc.h> 39 #include <sys/queue.h> 40 #include <sys/callout.h> 41 #include <sys/conf.h> 42 #include <sys/cpu.h> 43 #include <sys/device.h> 44 45 #include <sys/bus.h> 46 #include <sys/endian.h> 47 #include <sys/intr.h> 48 49 #include <net/bpf.h> 50 #include <net/if.h> 51 #include <net/if_arp.h> 52 #include <net/if_dl.h> 53 #include <net/if_ether.h> 54 #include <net/if_media.h> 55 #include <net/if_types.h> 56 57 #include <netinet/in.h> 58 #include <netinet/in_systm.h> 59 #include <netinet/in_var.h> 60 #include <netinet/ip.h> 61 62 #include <net80211/ieee80211_var.h> 63 #include <net80211/ieee80211_amrr.h> 64 #include <net80211/ieee80211_radiotap.h> 65 66 #include <dev/ic/athnreg.h> 67 #include <dev/ic/athnvar.h> 68 #include <dev/ic/arn5008.h> 69 #include <dev/ic/arn5416.h> 70 #include <dev/ic/arn9003.h> 71 #include <dev/ic/arn9280.h> 72 #include <dev/ic/arn9285.h> 73 #include <dev/ic/arn9287.h> 74 #include <dev/ic/arn9380.h> 75 76 #define Static static 77 78 #define IS_UP_AND_RUNNING(ifp) \ 79 (((ifp)->if_flags & IFF_UP) && ((ifp)->if_flags & IFF_RUNNING)) 80 81 #ifdef ATHN_DEBUG 82 int athn_debug = 0; 83 #endif 84 85 Static int athn_clock_rate(struct athn_softc *); 86 Static const char * 87 athn_get_mac_name(struct athn_softc *); 88 Static const char * 89 athn_get_rf_name(struct athn_softc *); 90 Static int athn_init(struct ifnet *); 91 Static int athn_init_calib(struct athn_softc *, 92 struct ieee80211_channel *, struct ieee80211_channel *); 93 Static int athn_ioctl(struct ifnet *, u_long, void *); 94 Static int athn_media_change(struct ifnet *); 95 Static int athn_newstate(struct ieee80211com *, enum ieee80211_state, 96 int); 97 Static struct ieee80211_node * 98 athn_node_alloc(struct ieee80211_node_table *); 99 Static int athn_reset_power_on(struct athn_softc *); 100 Static int athn_stop_rx_dma(struct athn_softc *); 101 Static int athn_switch_chan(struct athn_softc *, 102 struct ieee80211_channel *, struct ieee80211_channel *); 103 Static void athn_calib_to(void *); 104 Static void athn_disable_interrupts(struct athn_softc *); 105 Static void athn_enable_interrupts(struct athn_softc *); 106 Static void athn_get_chanlist(struct athn_softc *); 107 Static void athn_get_chipid(struct athn_softc *); 108 Static void athn_init_dma(struct athn_softc *); 109 Static void athn_init_qos(struct athn_softc *); 110 Static void athn_init_tx_queues(struct athn_softc *); 111 Static void athn_iter_func(void *, struct ieee80211_node *); 112 Static void athn_newassoc(struct ieee80211_node *, int); 113 Static void athn_next_scan(void *); 114 Static void athn_pmf_wlan_off(device_t self); 115 Static void athn_radiotap_attach(struct athn_softc *); 116 Static void athn_start(struct ifnet *); 117 Static void athn_tx_reclaim(struct athn_softc *, int); 118 Static void athn_watchdog(struct ifnet *); 119 Static void athn_write_serdes(struct athn_softc *, 120 const struct athn_serdes *); 121 Static void athn_softintr(void *); 122 123 #ifdef ATHN_BT_COEXISTENCE 124 Static void athn_btcoex_disable(struct athn_softc *); 125 Static void athn_btcoex_enable(struct athn_softc *); 126 #endif 127 128 #ifdef unused 129 Static int32_t athn_ani_get_rssi(struct athn_softc *); 130 Static int athn_rx_abort(struct athn_softc *); 131 #endif 132 133 #ifdef notyet 134 Static void athn_ani_cck_err_trigger(struct athn_softc *); 135 Static void athn_ani_lower_immunity(struct athn_softc *); 136 Static void athn_ani_monitor(struct athn_softc *); 137 Static void athn_ani_ofdm_err_trigger(struct athn_softc *); 138 Static void athn_ani_restart(struct athn_softc *); 139 #endif /* notyet */ 140 Static void athn_set_multi(struct athn_softc *); 141 142 PUBLIC int 143 athn_attach(struct athn_softc *sc) 144 { 145 struct ieee80211com *ic = &sc->sc_ic; 146 struct ifnet *ifp = &sc->sc_if; 147 size_t max_nnodes; 148 int error; 149 150 /* Read hardware revision. */ 151 athn_get_chipid(sc); 152 153 if ((error = athn_reset_power_on(sc)) != 0) { 154 aprint_error_dev(sc->sc_dev, "could not reset chip\n"); 155 return error; 156 } 157 158 if ((error = athn_set_power_awake(sc)) != 0) { 159 aprint_error_dev(sc->sc_dev, "could not wakeup chip\n"); 160 return error; 161 } 162 163 if (AR_SREV_5416(sc) || AR_SREV_9160(sc)) 164 error = ar5416_attach(sc); 165 else if (AR_SREV_9280(sc)) 166 error = ar9280_attach(sc); 167 else if (AR_SREV_9285(sc)) 168 error = ar9285_attach(sc); 169 #if NATHN_USB > 0 170 else if (AR_SREV_9271(sc)) 171 error = ar9285_attach(sc); 172 #endif 173 else if (AR_SREV_9287(sc)) 174 error = ar9287_attach(sc); 175 else if (AR_SREV_9380(sc) || AR_SREV_9485(sc)) 176 error = ar9380_attach(sc); 177 else 178 error = ENOTSUP; 179 if (error != 0) { 180 aprint_error_dev(sc->sc_dev, "could not attach chip\n"); 181 return error; 182 } 183 184 pmf_self_suspensor_init(sc->sc_dev, &sc->sc_suspensor, &sc->sc_qual); 185 pmf_event_register(sc->sc_dev, PMFE_RADIO_OFF, athn_pmf_wlan_off, 186 false); 187 188 /* We can put the chip in sleep state now. */ 189 athn_set_power_sleep(sc); 190 191 if (!(sc->sc_flags & ATHN_FLAG_USB)) { 192 sc->sc_soft_ih = softint_establish(SOFTINT_NET, athn_softintr, 193 sc); 194 if (sc->sc_soft_ih == NULL) { 195 aprint_error_dev(sc->sc_dev, 196 "could not establish softint\n"); 197 return EINVAL; 198 } 199 200 error = sc->sc_ops.dma_alloc(sc); 201 if (error != 0) { 202 aprint_error_dev(sc->sc_dev, 203 "could not allocate DMA resources\n"); 204 return error; 205 } 206 /* Steal one Tx buffer for beacons. */ 207 sc->sc_bcnbuf = SIMPLEQ_FIRST(&sc->sc_txbufs); 208 SIMPLEQ_REMOVE_HEAD(&sc->sc_txbufs, bf_list); 209 } 210 211 if (sc->sc_flags & ATHN_FLAG_RFSILENT) { 212 DPRINTFN(DBG_INIT, sc, 213 "found RF switch connected to GPIO pin %d\n", 214 sc->sc_rfsilent_pin); 215 } 216 DPRINTFN(DBG_INIT, sc, "%zd key cache entries\n", sc->sc_kc_entries); 217 218 /* 219 * In HostAP mode, the number of STAs that we can handle is 220 * limited by the number of entries in the HW key cache. 221 * TKIP keys consume 2 entries in the cache. 222 */ 223 KASSERT(sc->sc_kc_entries / 2 > IEEE80211_WEP_NKID); 224 max_nnodes = (sc->sc_kc_entries / 2) - IEEE80211_WEP_NKID; 225 if (sc->sc_max_aid != 0) /* we have an override */ 226 ic->ic_max_aid = sc->sc_max_aid; 227 if (ic->ic_max_aid > max_nnodes) 228 ic->ic_max_aid = max_nnodes; 229 230 DPRINTFN(DBG_INIT, sc, "using %s loop power control\n", 231 (sc->sc_flags & ATHN_FLAG_OLPC) ? "open" : "closed"); 232 DPRINTFN(DBG_INIT, sc, "txchainmask=0x%x rxchainmask=0x%x\n", 233 sc->sc_txchainmask, sc->sc_rxchainmask); 234 235 /* Count the number of bits set (in lowest 3 bits). */ 236 sc->sc_ntxchains = 237 ((sc->sc_txchainmask >> 2) & 1) + 238 ((sc->sc_txchainmask >> 1) & 1) + 239 ((sc->sc_txchainmask >> 0) & 1); 240 sc->sc_nrxchains = 241 ((sc->sc_rxchainmask >> 2) & 1) + 242 ((sc->sc_rxchainmask >> 1) & 1) + 243 ((sc->sc_rxchainmask >> 0) & 1); 244 245 if (AR_SINGLE_CHIP(sc)) { 246 aprint_normal(": Atheros %s\n", athn_get_mac_name(sc)); 247 aprint_verbose_dev(sc->sc_dev, 248 "rev %d (%dT%dR), ROM rev %d, address %s\n", 249 sc->sc_mac_rev, 250 sc->sc_ntxchains, sc->sc_nrxchains, sc->sc_eep_rev, 251 ether_sprintf(ic->ic_myaddr)); 252 } else { 253 aprint_normal(": Atheros %s, RF %s\n", athn_get_mac_name(sc), 254 athn_get_rf_name(sc)); 255 aprint_verbose_dev(sc->sc_dev, 256 "rev %d (%dT%dR), ROM rev %d, address %s\n", 257 sc->sc_mac_rev, 258 sc->sc_ntxchains, sc->sc_nrxchains, 259 sc->sc_eep_rev, ether_sprintf(ic->ic_myaddr)); 260 } 261 262 callout_init(&sc->sc_scan_to, 0); 263 callout_setfunc(&sc->sc_scan_to, athn_next_scan, sc); 264 callout_init(&sc->sc_calib_to, 0); 265 callout_setfunc(&sc->sc_calib_to, athn_calib_to, sc); 266 267 sc->sc_amrr.amrr_min_success_threshold = 1; 268 sc->sc_amrr.amrr_max_success_threshold = 15; 269 270 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 271 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 272 ic->ic_state = IEEE80211_S_INIT; 273 274 /* Set device capabilities. */ 275 ic->ic_caps = 276 IEEE80211_C_WPA | /* 802.11i */ 277 #ifndef IEEE80211_STA_ONLY 278 IEEE80211_C_HOSTAP | /* Host AP mode supported. */ 279 // XXX? IEEE80211_C_APPMGT | /* Host AP power saving supported. */ 280 #endif 281 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 282 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 283 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 284 IEEE80211_C_PMGT; /* Power saving supported. */ 285 286 #ifndef IEEE80211_NO_HT 287 if (sc->sc_flags & ATHN_FLAG_11N) { 288 int i, ntxstreams, nrxstreams; 289 290 /* Set HT capabilities. */ 291 ic->ic_htcaps = 292 IEEE80211_HTCAP_SMPS_DIS | 293 IEEE80211_HTCAP_CBW20_40 | 294 IEEE80211_HTCAP_SGI40 | 295 IEEE80211_HTCAP_DSSSCCK40; 296 if (AR_SREV_9271(sc) || AR_SREV_9287_10_OR_LATER(sc)) 297 ic->ic_htcaps |= IEEE80211_HTCAP_SGI20; 298 if (AR_SREV_9380_10_OR_LATER(sc)) 299 ic->ic_htcaps |= IEEE80211_HTCAP_LDPC; 300 if (AR_SREV_9280_10_OR_LATER(sc)) { 301 ic->ic_htcaps |= IEEE80211_HTCAP_TXSTBC; 302 ic->ic_htcaps |= 1 << IEEE80211_HTCAP_RXSTBC_SHIFT; 303 } 304 ntxstreams = sc->sc_ntxchains; 305 nrxstreams = sc->sc_nrxchains; 306 if (!AR_SREV_9380_10_OR_LATER(sc)) { 307 ntxstreams = MIN(ntxstreams, 2); 308 nrxstreams = MIN(nrxstreams, 2); 309 } 310 /* Set supported HT rates. */ 311 for (i = 0; i < nrxstreams; i++) 312 ic->ic_sup_mcs[i] = 0xff; 313 /* Set the "Tx MCS Set Defined" bit. */ 314 ic->ic_sup_mcs[12] |= 0x01; 315 if (ntxstreams != nrxstreams) { 316 /* Set "Tx Rx MCS Set Not Equal" bit. */ 317 ic->ic_sup_mcs[12] |= 0x02; 318 ic->ic_sup_mcs[12] |= (ntxstreams - 1) << 2; 319 } 320 } 321 #endif 322 323 /* Set supported rates. */ 324 if (sc->sc_flags & ATHN_FLAG_11G) { 325 ic->ic_sup_rates[IEEE80211_MODE_11B] = 326 ieee80211_std_rateset_11b; 327 ic->ic_sup_rates[IEEE80211_MODE_11G] = 328 ieee80211_std_rateset_11g; 329 } 330 if (sc->sc_flags & ATHN_FLAG_11A) { 331 ic->ic_sup_rates[IEEE80211_MODE_11A] = 332 ieee80211_std_rateset_11a; 333 } 334 335 /* Get the list of authorized/supported channels. */ 336 athn_get_chanlist(sc); 337 338 ifp->if_softc = sc; 339 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 340 if (!ifp->if_init) 341 ifp->if_init = athn_init; 342 if (!ifp->if_ioctl) 343 ifp->if_ioctl = athn_ioctl; 344 if (!ifp->if_start) 345 ifp->if_start = athn_start; 346 if (!ifp->if_watchdog) 347 ifp->if_watchdog = athn_watchdog; 348 IFQ_SET_READY(&ifp->if_snd); 349 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 350 351 if_initialize(ifp); 352 ieee80211_ifattach(ic); 353 /* Use common softint-based if_input */ 354 ifp->if_percpuq = if_percpuq_create(ifp); 355 if_register(ifp); 356 357 ic->ic_node_alloc = athn_node_alloc; 358 ic->ic_newassoc = athn_newassoc; 359 if (ic->ic_updateslot == NULL) 360 ic->ic_updateslot = athn_updateslot; 361 #ifdef notyet_edca 362 ic->ic_updateedca = athn_updateedca; 363 #endif 364 #ifdef notyet 365 ic->ic_set_key = athn_set_key; 366 ic->ic_delete_key = athn_delete_key; 367 #endif 368 369 /* Override 802.11 state transition machine. */ 370 sc->sc_newstate = ic->ic_newstate; 371 ic->ic_newstate = athn_newstate; 372 373 if (sc->sc_media_change == NULL) 374 sc->sc_media_change = athn_media_change; 375 ieee80211_media_init(ic, sc->sc_media_change, ieee80211_media_status); 376 377 athn_radiotap_attach(sc); 378 return 0; 379 } 380 381 PUBLIC void 382 athn_detach(struct athn_softc *sc) 383 { 384 struct ifnet *ifp = &sc->sc_if; 385 int qid; 386 387 callout_halt(&sc->sc_scan_to, NULL); 388 callout_halt(&sc->sc_calib_to, NULL); 389 390 if (!(sc->sc_flags & ATHN_FLAG_USB)) { 391 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 392 athn_tx_reclaim(sc, qid); 393 394 /* Free Tx/Rx DMA resources. */ 395 sc->sc_ops.dma_free(sc); 396 397 if (sc->sc_soft_ih != NULL) { 398 softint_disestablish(sc->sc_soft_ih); 399 sc->sc_soft_ih = NULL; 400 } 401 } 402 /* Free ROM copy. */ 403 if (sc->sc_eep != NULL) { 404 free(sc->sc_eep, M_DEVBUF); 405 sc->sc_eep = NULL; 406 } 407 408 bpf_detach(ifp); 409 ieee80211_ifdetach(&sc->sc_ic); 410 if_detach(ifp); 411 412 callout_destroy(&sc->sc_scan_to); 413 callout_destroy(&sc->sc_calib_to); 414 415 pmf_event_deregister(sc->sc_dev, PMFE_RADIO_OFF, athn_pmf_wlan_off, 416 false); 417 } 418 419 /* 420 * Attach the interface to 802.11 radiotap. 421 */ 422 Static void 423 athn_radiotap_attach(struct athn_softc *sc) 424 { 425 426 bpf_attach2(&sc->sc_if, DLT_IEEE802_11_RADIO, 427 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 428 &sc->sc_drvbpf); 429 430 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 431 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 432 sc->sc_rxtap.wr_ihdr.it_present = htole32(ATHN_RX_RADIOTAP_PRESENT); 433 434 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 435 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 436 sc->sc_txtap.wt_ihdr.it_present = htole32(ATHN_TX_RADIOTAP_PRESENT); 437 } 438 439 Static void 440 athn_get_chanlist(struct athn_softc *sc) 441 { 442 struct ieee80211com *ic = &sc->sc_ic; 443 uint8_t chan; 444 size_t i; 445 446 if (sc->sc_flags & ATHN_FLAG_11G) { 447 for (i = 1; i <= 14; i++) { 448 chan = i; 449 ic->ic_channels[chan].ic_freq = 450 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ); 451 ic->ic_channels[chan].ic_flags = 452 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 453 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 454 } 455 } 456 if (sc->sc_flags & ATHN_FLAG_11A) { 457 for (i = 0; i < __arraycount(athn_5ghz_chans); i++) { 458 chan = athn_5ghz_chans[i]; 459 ic->ic_channels[chan].ic_freq = 460 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 461 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 462 } 463 } 464 } 465 466 PUBLIC void 467 athn_rx_start(struct athn_softc *sc) 468 { 469 struct ieee80211com *ic = &sc->sc_ic; 470 uint32_t rfilt; 471 472 /* Setup Rx DMA descriptors. */ 473 sc->sc_ops.rx_enable(sc); 474 475 /* Set Rx filter. */ 476 rfilt = AR_RX_FILTER_UCAST | AR_RX_FILTER_BCAST | AR_RX_FILTER_MCAST; 477 #ifndef IEEE80211_NO_HT 478 /* Want Compressed Block Ack Requests. */ 479 rfilt |= AR_RX_FILTER_COMPR_BAR; 480 #endif 481 rfilt |= AR_RX_FILTER_BEACON; 482 if (ic->ic_opmode != IEEE80211_M_STA) { 483 rfilt |= AR_RX_FILTER_PROBEREQ; 484 if (ic->ic_opmode == IEEE80211_M_MONITOR) 485 rfilt |= AR_RX_FILTER_PROM; 486 #ifndef IEEE80211_STA_ONLY 487 if (AR_SREV_9280_10_OR_LATER(sc) && 488 ic->ic_opmode == IEEE80211_M_HOSTAP) 489 rfilt |= AR_RX_FILTER_PSPOLL; 490 #endif 491 } 492 athn_set_rxfilter(sc, rfilt); 493 494 /* Set BSSID mask. */ 495 AR_WRITE(sc, AR_BSSMSKL, 0xffffffff); 496 AR_WRITE(sc, AR_BSSMSKU, 0xffff); 497 498 athn_set_opmode(sc); 499 500 /* Set multicast filter. */ 501 AR_WRITE(sc, AR_MCAST_FIL0, 0xffffffff); 502 AR_WRITE(sc, AR_MCAST_FIL1, 0xffffffff); 503 504 AR_WRITE(sc, AR_FILT_OFDM, 0); 505 AR_WRITE(sc, AR_FILT_CCK, 0); 506 AR_WRITE(sc, AR_MIBC, 0); 507 AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 508 AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 509 510 /* XXX ANI. */ 511 AR_WRITE(sc, AR_PHY_ERR_1, 0); 512 AR_WRITE(sc, AR_PHY_ERR_2, 0); 513 514 /* Disable HW crypto for now. */ 515 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_ENCRYPT_DIS | AR_DIAG_DECRYPT_DIS); 516 517 /* Start PCU Rx. */ 518 AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 519 AR_WRITE_BARRIER(sc); 520 } 521 522 PUBLIC void 523 athn_set_rxfilter(struct athn_softc *sc, uint32_t rfilt) 524 { 525 526 AR_WRITE(sc, AR_RX_FILTER, rfilt); 527 #ifdef notyet 528 reg = AR_READ(sc, AR_PHY_ERR); 529 reg &= (AR_PHY_ERR_RADAR | AR_PHY_ERR_OFDM_TIMING | 530 AR_PHY_ERR_CCK_TIMING); 531 AR_WRITE(sc, AR_PHY_ERR, reg); 532 if (reg != 0) 533 AR_SETBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA); 534 else 535 AR_CLRBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA); 536 #else 537 AR_WRITE(sc, AR_PHY_ERR, 0); 538 AR_CLRBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA); 539 #endif 540 AR_WRITE_BARRIER(sc); 541 } 542 543 PUBLIC int 544 athn_intr(void *xsc) 545 { 546 struct athn_softc *sc = xsc; 547 struct ifnet *ifp = &sc->sc_if; 548 549 if (!IS_UP_AND_RUNNING(ifp)) 550 return 0; 551 552 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 553 /* 554 * The hardware is not ready/present, don't touch anything. 555 * Note this can happen early on if the IRQ is shared. 556 */ 557 return 0; 558 559 if (!sc->sc_ops.intr_status(sc)) 560 return 0; 561 562 AR_WRITE(sc, AR_INTR_ASYNC_MASK, 0); 563 AR_WRITE(sc, AR_INTR_SYNC_MASK, 0); 564 AR_WRITE_BARRIER(sc); 565 566 softint_schedule(sc->sc_soft_ih); 567 568 return 1; 569 } 570 571 Static void 572 athn_softintr(void *xsc) 573 { 574 struct athn_softc *sc = xsc; 575 struct ifnet *ifp = &sc->sc_if; 576 577 if (!IS_UP_AND_RUNNING(ifp)) 578 return; 579 580 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 581 /* 582 * The hardware is not ready/present, don't touch anything. 583 * Note this can happen early on if the IRQ is shared. 584 */ 585 return; 586 587 sc->sc_ops.intr(sc); 588 589 AR_WRITE(sc, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ); 590 AR_WRITE(sc, AR_INTR_SYNC_MASK, sc->sc_isync); 591 AR_WRITE_BARRIER(sc); 592 } 593 594 Static void 595 athn_get_chipid(struct athn_softc *sc) 596 { 597 uint32_t reg; 598 599 reg = AR_READ(sc, AR_SREV); 600 if (MS(reg, AR_SREV_ID) == 0xff) { 601 sc->sc_mac_ver = MS(reg, AR_SREV_VERSION2); 602 sc->sc_mac_rev = MS(reg, AR_SREV_REVISION2); 603 if (!(reg & AR_SREV_TYPE2_HOST_MODE)) 604 sc->sc_flags |= ATHN_FLAG_PCIE; 605 } else { 606 sc->sc_mac_ver = MS(reg, AR_SREV_VERSION); 607 sc->sc_mac_rev = MS(reg, AR_SREV_REVISION); 608 if (sc->sc_mac_ver == AR_SREV_VERSION_5416_PCIE) 609 sc->sc_flags |= ATHN_FLAG_PCIE; 610 } 611 } 612 613 Static const char * 614 athn_get_mac_name(struct athn_softc *sc) 615 { 616 617 switch (sc->sc_mac_ver) { 618 case AR_SREV_VERSION_5416_PCI: 619 return "AR5416"; 620 case AR_SREV_VERSION_5416_PCIE: 621 return "AR5418"; 622 case AR_SREV_VERSION_9160: 623 return "AR9160"; 624 case AR_SREV_VERSION_9280: 625 return "AR9280"; 626 case AR_SREV_VERSION_9285: 627 return "AR9285"; 628 case AR_SREV_VERSION_9271: 629 return "AR9271"; 630 case AR_SREV_VERSION_9287: 631 return "AR9287"; 632 case AR_SREV_VERSION_9380: 633 return "AR9380"; 634 case AR_SREV_VERSION_9485: 635 return "AR9485"; 636 default: 637 return "unknown"; 638 } 639 } 640 641 /* 642 * Return RF chip name (not for single-chip solutions). 643 */ 644 Static const char * 645 athn_get_rf_name(struct athn_softc *sc) 646 { 647 648 KASSERT(!AR_SINGLE_CHIP(sc)); 649 650 switch (sc->sc_rf_rev) { 651 case AR_RAD5133_SREV_MAJOR: /* Dual-band 3T3R. */ 652 return "AR5133"; 653 case AR_RAD2133_SREV_MAJOR: /* Single-band 3T3R. */ 654 return "AR2133"; 655 case AR_RAD5122_SREV_MAJOR: /* Dual-band 2T2R. */ 656 return "AR5122"; 657 case AR_RAD2122_SREV_MAJOR: /* Single-band 2T2R. */ 658 return "AR2122"; 659 default: 660 return "unknown"; 661 } 662 } 663 664 PUBLIC int 665 athn_reset_power_on(struct athn_softc *sc) 666 { 667 int ntries; 668 669 /* Set force wake. */ 670 AR_WRITE(sc, AR_RTC_FORCE_WAKE, 671 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 672 673 if (!AR_SREV_9380_10_OR_LATER(sc)) { 674 /* Make sure no DMA is active by doing an AHB reset. */ 675 AR_WRITE(sc, AR_RC, AR_RC_AHB); 676 } 677 /* RTC reset and clear. */ 678 AR_WRITE(sc, AR_RTC_RESET, 0); 679 AR_WRITE_BARRIER(sc); 680 DELAY(2); 681 if (!AR_SREV_9380_10_OR_LATER(sc)) 682 AR_WRITE(sc, AR_RC, 0); 683 AR_WRITE(sc, AR_RTC_RESET, 1); 684 685 /* Poll until RTC is ON. */ 686 for (ntries = 0; ntries < 1000; ntries++) { 687 if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == 688 AR_RTC_STATUS_ON) 689 break; 690 DELAY(10); 691 } 692 if (ntries == 1000) { 693 DPRINTFN(DBG_INIT, sc, "RTC not waking up\n"); 694 return ETIMEDOUT; 695 } 696 return athn_reset(sc, 0); 697 } 698 699 PUBLIC int 700 athn_reset(struct athn_softc *sc, int cold_reset) 701 { 702 int ntries; 703 704 /* Set force wake. */ 705 AR_WRITE(sc, AR_RTC_FORCE_WAKE, 706 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 707 708 if (AR_READ(sc, AR_INTR_SYNC_CAUSE) & 709 (AR_INTR_SYNC_LOCAL_TIMEOUT | AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { 710 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0); 711 AR_WRITE(sc, AR_RC, AR_RC_HOSTIF | 712 (!AR_SREV_9380_10_OR_LATER(sc) ? AR_RC_AHB : 0)); 713 } else if (!AR_SREV_9380_10_OR_LATER(sc)) 714 AR_WRITE(sc, AR_RC, AR_RC_AHB); 715 716 AR_WRITE(sc, AR_RTC_RC, AR_RTC_RC_MAC_WARM | 717 (cold_reset ? AR_RTC_RC_MAC_COLD : 0)); 718 AR_WRITE_BARRIER(sc); 719 DELAY(50); 720 AR_WRITE(sc, AR_RTC_RC, 0); 721 for (ntries = 0; ntries < 1000; ntries++) { 722 if (!(AR_READ(sc, AR_RTC_RC) & 723 (AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD))) 724 break; 725 DELAY(10); 726 } 727 if (ntries == 1000) { 728 DPRINTFN(DBG_INIT, sc, "RTC stuck in MAC reset\n"); 729 return ETIMEDOUT; 730 } 731 AR_WRITE(sc, AR_RC, 0); 732 AR_WRITE_BARRIER(sc); 733 return 0; 734 } 735 736 PUBLIC int 737 athn_set_power_awake(struct athn_softc *sc) 738 { 739 int ntries, error; 740 741 /* Do a Power-On-Reset if shutdown. */ 742 if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == 743 AR_RTC_STATUS_SHUTDOWN) { 744 if ((error = athn_reset_power_on(sc)) != 0) 745 return error; 746 if (!AR_SREV_9380_10_OR_LATER(sc)) 747 athn_init_pll(sc, NULL); 748 } 749 AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 750 AR_WRITE_BARRIER(sc); 751 DELAY(50); /* Give chip the chance to awake. */ 752 753 /* Poll until RTC is ON. */ 754 for (ntries = 0; ntries < 4000; ntries++) { 755 if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == 756 AR_RTC_STATUS_ON) 757 break; 758 DELAY(50); 759 AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 760 } 761 if (ntries == 4000) { 762 DPRINTFN(DBG_INIT, sc, "RTC not waking up\n"); 763 return ETIMEDOUT; 764 } 765 766 AR_CLRBITS(sc, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 767 AR_WRITE_BARRIER(sc); 768 return 0; 769 } 770 771 PUBLIC void 772 athn_set_power_sleep(struct athn_softc *sc) 773 { 774 775 AR_SETBITS(sc, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 776 /* Allow the MAC to go to sleep. */ 777 AR_CLRBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 778 if (!AR_SREV_9380_10_OR_LATER(sc)) 779 AR_WRITE(sc, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 780 /* 781 * NB: Clearing RTC_RESET_EN when setting the chip to sleep mode 782 * results in high power consumption on AR5416 chipsets. 783 */ 784 if (!AR_SREV_5416(sc) && !AR_SREV_9271(sc)) 785 AR_CLRBITS(sc, AR_RTC_RESET, AR_RTC_RESET_EN); 786 AR_WRITE_BARRIER(sc); 787 } 788 789 PUBLIC void 790 athn_init_pll(struct athn_softc *sc, const struct ieee80211_channel *c) 791 { 792 uint32_t pll; 793 794 if (AR_SREV_9380_10_OR_LATER(sc)) { 795 if (AR_SREV_9485(sc)) 796 AR_WRITE(sc, AR_RTC_PLL_CONTROL2, 0x886666); 797 pll = SM(AR_RTC_9160_PLL_REFDIV, 0x5); 798 pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c); 799 } else if (AR_SREV_9280_10_OR_LATER(sc)) { 800 pll = SM(AR_RTC_9160_PLL_REFDIV, 0x05); 801 if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) { 802 if (sc->sc_flags & ATHN_FLAG_FAST_PLL_CLOCK) 803 pll = 0x142c; 804 else if (AR_SREV_9280_20(sc)) 805 pll = 0x2850; 806 else 807 pll |= SM(AR_RTC_9160_PLL_DIV, 0x28); 808 } else 809 pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c); 810 } else if (AR_SREV_9160_10_OR_LATER(sc)) { 811 pll = SM(AR_RTC_9160_PLL_REFDIV, 0x05); 812 if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) 813 pll |= SM(AR_RTC_9160_PLL_DIV, 0x50); 814 else 815 pll |= SM(AR_RTC_9160_PLL_DIV, 0x58); 816 } else { 817 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; 818 if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) 819 pll |= SM(AR_RTC_PLL_DIV, 0x0a); 820 else 821 pll |= SM(AR_RTC_PLL_DIV, 0x0b); 822 } 823 DPRINTFN(DBG_INIT, sc, "AR_RTC_PLL_CONTROL=0x%08x\n", pll); 824 AR_WRITE(sc, AR_RTC_PLL_CONTROL, pll); 825 if (AR_SREV_9271(sc)) { 826 /* Switch core clock to 117MHz. */ 827 AR_WRITE_BARRIER(sc); 828 DELAY(500); 829 AR_WRITE(sc, 0x50050, 0x304); 830 } 831 AR_WRITE_BARRIER(sc); 832 DELAY(100); 833 AR_WRITE(sc, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 834 AR_WRITE_BARRIER(sc); 835 } 836 837 Static void 838 athn_write_serdes(struct athn_softc *sc, const struct athn_serdes *serdes) 839 { 840 int i; 841 842 /* Write sequence to Serializer/Deserializer. */ 843 for (i = 0; i < serdes->nvals; i++) 844 AR_WRITE(sc, serdes->regs[i], serdes->vals[i]); 845 AR_WRITE_BARRIER(sc); 846 } 847 848 PUBLIC void 849 athn_config_pcie(struct athn_softc *sc) 850 { 851 852 /* Disable PLL when in L0s as well as receiver clock when in L1. */ 853 athn_write_serdes(sc, sc->sc_serdes); 854 855 DELAY(1000); 856 /* Allow forcing of PCIe core into L1 state. */ 857 AR_SETBITS(sc, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 858 859 #ifndef ATHN_PCIE_WAEN 860 AR_WRITE(sc, AR_WA, sc->sc_workaround); 861 #else 862 AR_WRITE(sc, AR_WA, ATHN_PCIE_WAEN); 863 #endif 864 AR_WRITE_BARRIER(sc); 865 } 866 867 /* 868 * Serializer/Deserializer programming for non-PCIe devices. 869 */ 870 static const uint32_t ar_nonpcie_serdes_regs[] = { 871 AR_PCIE_SERDES, 872 AR_PCIE_SERDES, 873 AR_PCIE_SERDES, 874 AR_PCIE_SERDES, 875 AR_PCIE_SERDES, 876 AR_PCIE_SERDES, 877 AR_PCIE_SERDES, 878 AR_PCIE_SERDES, 879 AR_PCIE_SERDES, 880 AR_PCIE_SERDES2, 881 }; 882 883 static const uint32_t ar_nonpcie_serdes_vals[] = { 884 0x9248fc00, 885 0x24924924, 886 0x28000029, 887 0x57160824, 888 0x25980579, 889 0x00000000, 890 0x1aaabe40, 891 0xbe105554, 892 0x000e1007, 893 0x00000000 894 }; 895 896 static const struct athn_serdes ar_nonpcie_serdes = { 897 __arraycount(ar_nonpcie_serdes_vals), 898 ar_nonpcie_serdes_regs, 899 ar_nonpcie_serdes_vals 900 }; 901 902 PUBLIC void 903 athn_config_nonpcie(struct athn_softc *sc) 904 { 905 906 athn_write_serdes(sc, &ar_nonpcie_serdes); 907 } 908 909 PUBLIC int 910 athn_set_chan(struct athn_softc *sc, struct ieee80211_channel *curchan, 911 struct ieee80211_channel *extchan) 912 { 913 struct athn_ops *ops = &sc->sc_ops; 914 int error, qid; 915 916 /* Check that Tx is stopped, otherwise RF Bus grant will not work. */ 917 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 918 if (athn_tx_pending(sc, qid)) 919 return EBUSY; 920 921 /* Request RF Bus grant. */ 922 if ((error = ops->rf_bus_request(sc)) != 0) 923 return error; 924 925 ops->set_phy(sc, curchan, extchan); 926 927 /* Change the synthesizer. */ 928 if ((error = ops->set_synth(sc, curchan, extchan)) != 0) 929 return error; 930 931 sc->sc_curchan = curchan; 932 sc->sc_curchanext = extchan; 933 934 /* Set transmit power values for new channel. */ 935 ops->set_txpower(sc, curchan, extchan); 936 937 /* Release the RF Bus grant. */ 938 ops->rf_bus_release(sc); 939 940 /* Write delta slope coeffs for modes where OFDM may be used. */ 941 if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11B) 942 ops->set_delta_slope(sc, curchan, extchan); 943 944 ops->spur_mitigate(sc, curchan, extchan); 945 /* XXX Load noisefloor values and start calibration. */ 946 947 return 0; 948 } 949 950 Static int 951 athn_switch_chan(struct athn_softc *sc, struct ieee80211_channel *curchan, 952 struct ieee80211_channel *extchan) 953 { 954 int error, qid; 955 956 /* Disable interrupts. */ 957 athn_disable_interrupts(sc); 958 959 /* Stop all Tx queues. */ 960 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 961 athn_stop_tx_dma(sc, qid); 962 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 963 athn_tx_reclaim(sc, qid); 964 965 /* Stop Rx. */ 966 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 967 AR_WRITE(sc, AR_MIBC, AR_MIBC_FMC); 968 AR_WRITE(sc, AR_MIBC, AR_MIBC_CMC); 969 AR_WRITE(sc, AR_FILT_OFDM, 0); 970 AR_WRITE(sc, AR_FILT_CCK, 0); 971 athn_set_rxfilter(sc, 0); 972 error = athn_stop_rx_dma(sc); 973 if (error != 0) 974 goto reset; 975 976 #ifdef notyet 977 /* AR9280 needs a full reset. */ 978 if (AR_SREV_9280(sc)) 979 #endif 980 goto reset; 981 982 /* If band or bandwidth changes, we need to do a full reset. */ 983 if (curchan->ic_flags != sc->sc_curchan->ic_flags || 984 ((extchan != NULL) ^ (sc->sc_curchanext != NULL))) { 985 DPRINTFN(DBG_RF, sc, "channel band switch\n"); 986 goto reset; 987 } 988 error = athn_set_power_awake(sc); 989 if (error != 0) 990 goto reset; 991 992 error = athn_set_chan(sc, curchan, extchan); 993 if (error != 0) { 994 reset: /* Error found, try a full reset. */ 995 DPRINTFN(DBG_RF, sc, "needs a full reset\n"); 996 error = athn_hw_reset(sc, curchan, extchan, 0); 997 if (error != 0) /* Hopeless case. */ 998 return error; 999 } 1000 athn_rx_start(sc); 1001 1002 /* Re-enable interrupts. */ 1003 athn_enable_interrupts(sc); 1004 return 0; 1005 } 1006 1007 PUBLIC void 1008 athn_get_delta_slope(uint32_t coeff, uint32_t *exponent, uint32_t *mantissa) 1009 { 1010 #define COEFF_SCALE_SHIFT 24 1011 uint32_t exp, man; 1012 1013 /* exponent = 14 - floor(log2(coeff)) */ 1014 for (exp = 31; exp > 0; exp--) 1015 if (coeff & (1U << exp)) 1016 break; 1017 exp = 14 - (exp - COEFF_SCALE_SHIFT); 1018 1019 /* mantissa = floor(coeff * 2^exponent + 0.5) */ 1020 man = coeff + (1 << (COEFF_SCALE_SHIFT - exp - 1)); 1021 1022 *mantissa = man >> (COEFF_SCALE_SHIFT - exp); 1023 *exponent = exp - 16; 1024 #undef COEFF_SCALE_SHIFT 1025 } 1026 1027 PUBLIC void 1028 athn_reset_key(struct athn_softc *sc, int entry) 1029 { 1030 1031 /* 1032 * NB: Key cache registers access special memory area that requires 1033 * two 32-bit writes to actually update the values in the internal 1034 * memory. Consequently, writes must be grouped by pair. 1035 */ 1036 AR_WRITE(sc, AR_KEYTABLE_KEY0(entry), 0); 1037 AR_WRITE(sc, AR_KEYTABLE_KEY1(entry), 0); 1038 1039 AR_WRITE(sc, AR_KEYTABLE_KEY2(entry), 0); 1040 AR_WRITE(sc, AR_KEYTABLE_KEY3(entry), 0); 1041 1042 AR_WRITE(sc, AR_KEYTABLE_KEY4(entry), 0); 1043 AR_WRITE(sc, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR); 1044 1045 AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), 0); 1046 AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), 0); 1047 1048 AR_WRITE_BARRIER(sc); 1049 } 1050 1051 #ifdef notyet 1052 Static int 1053 athn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1054 struct ieee80211_key *k) 1055 { 1056 struct athn_softc *sc = ic->ic_ifp->if_softc; 1057 const uint8_t *txmic, *rxmic, *key, *addr; 1058 uintptr_t entry, micentry; 1059 uint32_t type, lo, hi; 1060 1061 switch (k->k_cipher) { 1062 case IEEE80211_CIPHER_WEP40: 1063 type = AR_KEYTABLE_TYPE_40; 1064 break; 1065 case IEEE80211_CIPHER_WEP104: 1066 type = AR_KEYTABLE_TYPE_104; 1067 break; 1068 case IEEE80211_CIPHER_TKIP: 1069 type = AR_KEYTABLE_TYPE_TKIP; 1070 break; 1071 case IEEE80211_CIPHER_CCMP: 1072 type = AR_KEYTABLE_TYPE_CCM; 1073 break; 1074 default: 1075 /* Fallback to software crypto for other ciphers. */ 1076 return ieee80211_set_key(ic, ni, k); 1077 } 1078 1079 if (!(k->k_flags & IEEE80211_KEY_GROUP)) 1080 entry = IEEE80211_WEP_NKID + IEEE80211_AID(ni->ni_associd); 1081 else 1082 entry = k->k_id; 1083 k->k_priv = (void *)entry; 1084 1085 /* NB: See note about key cache registers access above. */ 1086 key = k->k_key; 1087 if (type == AR_KEYTABLE_TYPE_TKIP) { 1088 #ifndef IEEE80211_STA_ONLY 1089 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1090 txmic = &key[16]; 1091 rxmic = &key[24]; 1092 } else 1093 #endif 1094 { 1095 rxmic = &key[16]; 1096 txmic = &key[24]; 1097 } 1098 /* Tx+Rx MIC key is at entry + 64. */ 1099 micentry = entry + 64; 1100 AR_WRITE(sc, AR_KEYTABLE_KEY0(micentry), LE_READ_4(&rxmic[0])); 1101 AR_WRITE(sc, AR_KEYTABLE_KEY1(micentry), LE_READ_2(&txmic[2])); 1102 1103 AR_WRITE(sc, AR_KEYTABLE_KEY2(micentry), LE_READ_4(&rxmic[4])); 1104 AR_WRITE(sc, AR_KEYTABLE_KEY3(micentry), LE_READ_2(&txmic[0])); 1105 1106 AR_WRITE(sc, AR_KEYTABLE_KEY4(micentry), LE_READ_4(&txmic[4])); 1107 AR_WRITE(sc, AR_KEYTABLE_TYPE(micentry), AR_KEYTABLE_TYPE_CLR); 1108 } 1109 AR_WRITE(sc, AR_KEYTABLE_KEY0(entry), LE_READ_4(&key[ 0])); 1110 AR_WRITE(sc, AR_KEYTABLE_KEY1(entry), LE_READ_2(&key[ 4])); 1111 1112 AR_WRITE(sc, AR_KEYTABLE_KEY2(entry), LE_READ_4(&key[ 6])); 1113 AR_WRITE(sc, AR_KEYTABLE_KEY3(entry), LE_READ_2(&key[10])); 1114 1115 AR_WRITE(sc, AR_KEYTABLE_KEY4(entry), LE_READ_4(&key[12])); 1116 AR_WRITE(sc, AR_KEYTABLE_TYPE(entry), type); 1117 1118 if (!(k->k_flags & IEEE80211_KEY_GROUP)) { 1119 addr = ni->ni_macaddr; 1120 lo = LE_READ_4(&addr[0]); 1121 hi = LE_READ_2(&addr[4]); 1122 lo = lo >> 1 | hi << 31; 1123 hi = hi >> 1; 1124 } else 1125 lo = hi = 0; 1126 AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), lo); 1127 AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), hi | AR_KEYTABLE_VALID); 1128 AR_WRITE_BARRIER(sc); 1129 return 0; 1130 } 1131 1132 Static void 1133 athn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1134 struct ieee80211_key *k) 1135 { 1136 struct athn_softc *sc = ic->ic_ifp->if_softc; 1137 uintptr_t entry; 1138 1139 switch (k->k_cipher) { 1140 case IEEE80211_CIPHER_WEP40: 1141 case IEEE80211_CIPHER_WEP104: 1142 case IEEE80211_CIPHER_CCMP: 1143 entry = (uintptr_t)k->k_priv; 1144 athn_reset_key(sc, entry); 1145 break; 1146 case IEEE80211_CIPHER_TKIP: 1147 entry = (uintptr_t)k->k_priv; 1148 athn_reset_key(sc, entry); 1149 athn_reset_key(sc, entry + 64); 1150 break; 1151 default: 1152 /* Fallback to software crypto for other ciphers. */ 1153 ieee80211_delete_key(ic, ni, k); 1154 } 1155 } 1156 #endif /* notyet */ 1157 1158 PUBLIC void 1159 athn_led_init(struct athn_softc *sc) 1160 { 1161 struct athn_ops *ops = &sc->sc_ops; 1162 1163 ops->gpio_config_output(sc, sc->sc_led_pin, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1164 /* LED off, active low. */ 1165 athn_set_led(sc, 0); 1166 } 1167 1168 PUBLIC void 1169 athn_set_led(struct athn_softc *sc, int on) 1170 { 1171 struct athn_ops *ops = &sc->sc_ops; 1172 1173 sc->sc_led_state = on; 1174 ops->gpio_write(sc, sc->sc_led_pin, !sc->sc_led_state); 1175 } 1176 1177 #ifdef ATHN_BT_COEXISTENCE 1178 Static void 1179 athn_btcoex_init(struct athn_softc *sc) 1180 { 1181 struct athn_ops *ops = &sc->sc_ops; 1182 uint32_t reg; 1183 1184 if (sc->sc_flags & ATHN_FLAG_BTCOEX2WIRE) { 1185 /* Connect bt_active to baseband. */ 1186 AR_CLRBITS(sc, sc->sc_gpio_input_en_off, 1187 AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF | 1188 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF); 1189 AR_SETBITS(sc, sc->sc_gpio_input_en_off, 1190 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB); 1191 1192 reg = AR_READ(sc, AR_GPIO_INPUT_MUX1); 1193 reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE, 1194 AR_GPIO_BTACTIVE_PIN); 1195 AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg); 1196 AR_WRITE_BARRIER(sc); 1197 1198 ops->gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN); 1199 } else { /* 3-wire. */ 1200 AR_SETBITS(sc, sc->sc_gpio_input_en_off, 1201 AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB | 1202 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB); 1203 1204 reg = AR_READ(sc, AR_GPIO_INPUT_MUX1); 1205 reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE, 1206 AR_GPIO_BTACTIVE_PIN); 1207 reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_PRIORITY, 1208 AR_GPIO_BTPRIORITY_PIN); 1209 AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg); 1210 AR_WRITE_BARRIER(sc); 1211 1212 ops->gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN); 1213 ops->gpio_config_input(sc, AR_GPIO_BTPRIORITY_PIN); 1214 } 1215 } 1216 1217 Static void 1218 athn_btcoex_enable(struct athn_softc *sc) 1219 { 1220 struct athn_ops *ops = &sc->sc_ops; 1221 uint32_t reg; 1222 1223 if (sc->sc_flags & ATHN_FLAG_BTCOEX3WIRE) { 1224 AR_WRITE(sc, AR_BT_COEX_MODE, 1225 SM(AR_BT_MODE, AR_BT_MODE_SLOTTED) | 1226 SM(AR_BT_PRIORITY_TIME, 2) | 1227 SM(AR_BT_FIRST_SLOT_TIME, 5) | 1228 SM(AR_BT_QCU_THRESH, ATHN_QID_AC_BE) | 1229 AR_BT_TXSTATE_EXTEND | AR_BT_TX_FRAME_EXTEND | 1230 AR_BT_QUIET | AR_BT_RX_CLEAR_POLARITY); 1231 AR_WRITE(sc, AR_BT_COEX_WEIGHT, 1232 SM(AR_BTCOEX_BT_WGHT, AR_STOMP_LOW_BT_WGHT) | 1233 SM(AR_BTCOEX_WL_WGHT, AR_STOMP_LOW_WL_WGHT)); 1234 AR_WRITE(sc, AR_BT_COEX_MODE2, 1235 SM(AR_BT_BCN_MISS_THRESH, 50) | 1236 AR_BT_HOLD_RX_CLEAR | AR_BT_DISABLE_BT_ANT); 1237 1238 AR_SETBITS(sc, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE); 1239 AR_CLRBITS(sc, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX); 1240 AR_WRITE_BARRIER(sc); 1241 1242 ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN, 1243 AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL); 1244 1245 } else { /* 2-wire. */ 1246 ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN, 1247 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME); 1248 } 1249 reg = AR_READ(sc, AR_GPIO_PDPU); 1250 reg &= ~(0x3 << (AR_GPIO_WLANACTIVE_PIN * 2)); 1251 reg |= 0x2 << (AR_GPIO_WLANACTIVE_PIN * 2); 1252 AR_WRITE(sc, AR_GPIO_PDPU, reg); 1253 AR_WRITE_BARRIER(sc); 1254 1255 /* Disable PCIe Active State Power Management (ASPM). */ 1256 if (sc->sc_disable_aspm != NULL) 1257 sc->sc_disable_aspm(sc); 1258 1259 /* XXX Start periodic timer. */ 1260 } 1261 1262 Static void 1263 athn_btcoex_disable(struct athn_softc *sc) 1264 { 1265 struct athn_ops *ops = &sc->sc_ops; 1266 1267 ops->gpio_write(sc, AR_GPIO_WLANACTIVE_PIN, 0); 1268 1269 ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN, 1270 AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1271 1272 if (sc->sc_flags & ATHN_FLAG_BTCOEX3WIRE) { 1273 AR_WRITE(sc, AR_BT_COEX_MODE, 1274 SM(AR_BT_MODE, AR_BT_MODE_DISABLED) | AR_BT_QUIET); 1275 AR_WRITE(sc, AR_BT_COEX_WEIGHT, 0); 1276 AR_WRITE(sc, AR_BT_COEX_MODE2, 0); 1277 /* XXX Stop periodic timer. */ 1278 } 1279 AR_WRITE_BARRIER(sc); 1280 /* XXX Restore ASPM setting? */ 1281 } 1282 #endif 1283 1284 Static void 1285 athn_iter_func(void *arg, struct ieee80211_node *ni) 1286 { 1287 struct athn_softc *sc = arg; 1288 struct athn_node *an = (struct athn_node *)ni; 1289 1290 ieee80211_amrr_choose(&sc->sc_amrr, ni, &an->amn); 1291 } 1292 1293 Static void 1294 athn_calib_to(void *arg) 1295 { 1296 struct athn_softc *sc = arg; 1297 struct athn_ops *ops = &sc->sc_ops; 1298 struct ieee80211com *ic = &sc->sc_ic; 1299 int s; 1300 1301 s = splnet(); 1302 1303 /* Do periodic (every 4 minutes) PA calibration. */ 1304 if (AR_SREV_9285_11_OR_LATER(sc) && 1305 !AR_SREV_9380_10_OR_LATER(sc) && 1306 (ticks - (sc->sc_pa_calib_ticks + 240 * hz)) >= 0) { 1307 sc->sc_pa_calib_ticks = ticks; 1308 if (AR_SREV_9271(sc)) 1309 ar9271_pa_calib(sc); 1310 else 1311 ar9285_pa_calib(sc); 1312 } 1313 1314 /* Do periodic (every 30 seconds) temperature compensation. */ 1315 if ((sc->sc_flags & ATHN_FLAG_OLPC) && 1316 ticks >= sc->sc_olpc_ticks + 30 * hz) { 1317 sc->sc_olpc_ticks = ticks; 1318 ops->olpc_temp_compensation(sc); 1319 } 1320 1321 #ifdef notyet 1322 /* XXX ANI. */ 1323 athn_ani_monitor(sc); 1324 1325 ops->next_calib(sc); 1326 #endif 1327 if (ic->ic_fixed_rate == -1) { 1328 if (ic->ic_opmode == IEEE80211_M_STA) 1329 athn_iter_func(sc, ic->ic_bss); 1330 else 1331 ieee80211_iterate_nodes(&ic->ic_sta, athn_iter_func, sc); 1332 } 1333 callout_schedule(&sc->sc_calib_to, hz / 2); 1334 splx(s); 1335 } 1336 1337 Static int 1338 athn_init_calib(struct athn_softc *sc, struct ieee80211_channel *curchan, 1339 struct ieee80211_channel *extchan) 1340 { 1341 struct athn_ops *ops = &sc->sc_ops; 1342 int error; 1343 1344 if (AR_SREV_9380_10_OR_LATER(sc)) 1345 error = ar9003_init_calib(sc); 1346 else if (AR_SREV_9285_10_OR_LATER(sc)) 1347 error = ar9285_init_calib(sc, curchan, extchan); 1348 else 1349 error = ar5416_init_calib(sc, curchan, extchan); 1350 if (error != 0) 1351 return error; 1352 1353 if (!AR_SREV_9380_10_OR_LATER(sc)) { 1354 /* Do PA calibration. */ 1355 if (AR_SREV_9285_11_OR_LATER(sc)) { 1356 sc->sc_pa_calib_ticks = ticks; 1357 if (AR_SREV_9271(sc)) 1358 ar9271_pa_calib(sc); 1359 else 1360 ar9285_pa_calib(sc); 1361 } 1362 /* Do noisefloor calibration. */ 1363 ops->noisefloor_calib(sc); 1364 } 1365 if (AR_SREV_9160_10_OR_LATER(sc)) { 1366 /* Support IQ calibration. */ 1367 sc->sc_sup_calib_mask = ATHN_CAL_IQ; 1368 if (AR_SREV_9380_10_OR_LATER(sc)) { 1369 /* Support temperature compensation calibration. */ 1370 sc->sc_sup_calib_mask |= ATHN_CAL_TEMP; 1371 } else if (IEEE80211_IS_CHAN_5GHZ(curchan) || extchan != NULL) { 1372 /* 1373 * ADC gain calibration causes uplink throughput 1374 * drops in HT40 mode on AR9287. 1375 */ 1376 if (!AR_SREV_9287(sc)) { 1377 /* Support ADC gain calibration. */ 1378 sc->sc_sup_calib_mask |= ATHN_CAL_ADC_GAIN; 1379 } 1380 /* Support ADC DC offset calibration. */ 1381 sc->sc_sup_calib_mask |= ATHN_CAL_ADC_DC; 1382 } 1383 } 1384 return 0; 1385 } 1386 1387 /* 1388 * Adaptive noise immunity. 1389 */ 1390 #ifdef notyet 1391 Static int32_t 1392 athn_ani_get_rssi(struct athn_softc *sc) 1393 { 1394 1395 return 0; /* XXX */ 1396 } 1397 #endif /* notyet */ 1398 1399 #ifdef notyet 1400 Static void 1401 athn_ani_ofdm_err_trigger(struct athn_softc *sc) 1402 { 1403 struct athn_ani *ani = &sc->sc_ani; 1404 struct athn_ops *ops = &sc->sc_ops; 1405 int32_t rssi; 1406 1407 /* First, raise noise immunity level, up to max. */ 1408 if (ani->noise_immunity_level < 4) { 1409 ani->noise_immunity_level++; 1410 ops->set_noise_immunity_level(sc, ani->noise_immunity_level); 1411 return; 1412 } 1413 1414 /* Then, raise our spur immunity level, up to max. */ 1415 if (ani->spur_immunity_level < 7) { 1416 ani->spur_immunity_level++; 1417 ops->set_spur_immunity_level(sc, ani->spur_immunity_level); 1418 return; 1419 } 1420 1421 #ifndef IEEE80211_STA_ONLY 1422 if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { 1423 if (ani->firstep_level < 2) { 1424 ani->firstep_level++; 1425 ops->set_firstep_level(sc, ani->firstep_level); 1426 } 1427 return; 1428 } 1429 #endif 1430 rssi = athn_ani_get_rssi(sc); 1431 if (rssi > ATHN_ANI_RSSI_THR_HIGH) { 1432 /* 1433 * Beacon RSSI is high, turn off OFDM weak signal detection 1434 * or raise first step level as last resort. 1435 */ 1436 if (ani->ofdm_weak_signal) { 1437 ani->ofdm_weak_signal = 0; 1438 ops->disable_ofdm_weak_signal(sc); 1439 ani->spur_immunity_level = 0; 1440 ops->set_spur_immunity_level(sc, 0); 1441 } else if (ani->firstep_level < 2) { 1442 ani->firstep_level++; 1443 ops->set_firstep_level(sc, ani->firstep_level); 1444 } 1445 } else if (rssi > ATHN_ANI_RSSI_THR_LOW) { 1446 /* 1447 * Beacon RSSI is in mid range, we need OFDM weak signal 1448 * detection but we can raise first step level. 1449 */ 1450 if (!ani->ofdm_weak_signal) { 1451 ani->ofdm_weak_signal = 1; 1452 ops->enable_ofdm_weak_signal(sc); 1453 } 1454 if (ani->firstep_level < 2) { 1455 ani->firstep_level++; 1456 ops->set_firstep_level(sc, ani->firstep_level); 1457 } 1458 } else if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) { 1459 /* 1460 * Beacon RSSI is low, if in b/g mode, turn off OFDM weak 1461 * signal detection and zero first step level to maximize 1462 * CCK sensitivity. 1463 */ 1464 if (ani->ofdm_weak_signal) { 1465 ani->ofdm_weak_signal = 0; 1466 ops->disable_ofdm_weak_signal(sc); 1467 } 1468 if (ani->firstep_level > 0) { 1469 ani->firstep_level = 0; 1470 ops->set_firstep_level(sc, 0); 1471 } 1472 } 1473 } 1474 #endif /* notyet */ 1475 1476 #ifdef notyet 1477 Static void 1478 athn_ani_cck_err_trigger(struct athn_softc *sc) 1479 { 1480 struct athn_ani *ani = &sc->sc_ani; 1481 struct athn_ops *ops = &sc->sc_ops; 1482 int32_t rssi; 1483 1484 /* Raise noise immunity level, up to max. */ 1485 if (ani->noise_immunity_level < 4) { 1486 ani->noise_immunity_level++; 1487 ops->set_noise_immunity_level(sc, ani->noise_immunity_level); 1488 return; 1489 } 1490 1491 #ifndef IEEE80211_STA_ONLY 1492 if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { 1493 if (ani->firstep_level < 2) { 1494 ani->firstep_level++; 1495 ops->set_firstep_level(sc, ani->firstep_level); 1496 } 1497 return; 1498 } 1499 #endif 1500 rssi = athn_ani_get_rssi(sc); 1501 if (rssi > ATHN_ANI_RSSI_THR_LOW) { 1502 /* 1503 * Beacon RSSI is in mid or high range, raise first step 1504 * level. 1505 */ 1506 if (ani->firstep_level < 2) { 1507 ani->firstep_level++; 1508 ops->set_firstep_level(sc, ani->firstep_level); 1509 } 1510 } else if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) { 1511 /* 1512 * Beacon RSSI is low, zero first step level to maximize 1513 * CCK sensitivity. 1514 */ 1515 if (ani->firstep_level > 0) { 1516 ani->firstep_level = 0; 1517 ops->set_firstep_level(sc, 0); 1518 } 1519 } 1520 } 1521 #endif /* notyet */ 1522 1523 #ifdef notyet 1524 Static void 1525 athn_ani_lower_immunity(struct athn_softc *sc) 1526 { 1527 struct athn_ani *ani = &sc->sc_ani; 1528 struct athn_ops *ops = &sc->sc_ops; 1529 int32_t rssi; 1530 1531 #ifndef IEEE80211_STA_ONLY 1532 if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) { 1533 if (ani->firstep_level > 0) { 1534 ani->firstep_level--; 1535 ops->set_firstep_level(sc, ani->firstep_level); 1536 } 1537 return; 1538 } 1539 #endif 1540 rssi = athn_ani_get_rssi(sc); 1541 if (rssi > ATHN_ANI_RSSI_THR_HIGH) { 1542 /* 1543 * Beacon RSSI is high, leave OFDM weak signal detection 1544 * off or it may oscillate. 1545 */ 1546 } else if (rssi > ATHN_ANI_RSSI_THR_LOW) { 1547 /* 1548 * Beacon RSSI is in mid range, turn on OFDM weak signal 1549 * detection or lower first step level. 1550 */ 1551 if (!ani->ofdm_weak_signal) { 1552 ani->ofdm_weak_signal = 1; 1553 ops->enable_ofdm_weak_signal(sc); 1554 return; 1555 } 1556 if (ani->firstep_level > 0) { 1557 ani->firstep_level--; 1558 ops->set_firstep_level(sc, ani->firstep_level); 1559 return; 1560 } 1561 } else { 1562 /* Beacon RSSI is low, lower first step level. */ 1563 if (ani->firstep_level > 0) { 1564 ani->firstep_level--; 1565 ops->set_firstep_level(sc, ani->firstep_level); 1566 return; 1567 } 1568 } 1569 /* 1570 * Lower spur immunity level down to zero, or if all else fails, 1571 * lower noise immunity level down to zero. 1572 */ 1573 if (ani->spur_immunity_level > 0) { 1574 ani->spur_immunity_level--; 1575 ops->set_spur_immunity_level(sc, ani->spur_immunity_level); 1576 } else if (ani->noise_immunity_level > 0) { 1577 ani->noise_immunity_level--; 1578 ops->set_noise_immunity_level(sc, ani->noise_immunity_level); 1579 } 1580 } 1581 #endif /* notyet */ 1582 1583 #ifdef notyet 1584 Static void 1585 athn_ani_restart(struct athn_softc *sc) 1586 { 1587 struct athn_ani *ani = &sc->sc_ani; 1588 1589 AR_WRITE(sc, AR_PHY_ERR_1, 0); 1590 AR_WRITE(sc, AR_PHY_ERR_2, 0); 1591 AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 1592 AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 1593 AR_WRITE_BARRIER(sc); 1594 1595 ani->listen_time = 0; 1596 ani->ofdm_phy_err_count = 0; 1597 ani->cck_phy_err_count = 0; 1598 } 1599 #endif /* notyet */ 1600 1601 #ifdef notyet 1602 Static void 1603 athn_ani_monitor(struct athn_softc *sc) 1604 { 1605 struct athn_ani *ani = &sc->sc_ani; 1606 uint32_t cyccnt, txfcnt, rxfcnt, phy1, phy2; 1607 int32_t cycdelta, txfdelta, rxfdelta; 1608 int32_t listen_time; 1609 1610 txfcnt = AR_READ(sc, AR_TFCNT); /* Tx frame count. */ 1611 rxfcnt = AR_READ(sc, AR_RFCNT); /* Rx frame count. */ 1612 cyccnt = AR_READ(sc, AR_CCCNT); /* Cycle count. */ 1613 1614 if (ani->cyccnt != 0 && ani->cyccnt <= cyccnt) { 1615 cycdelta = cyccnt - ani->cyccnt; 1616 txfdelta = txfcnt - ani->txfcnt; 1617 rxfdelta = rxfcnt - ani->rxfcnt; 1618 1619 listen_time = (cycdelta - txfdelta - rxfdelta) / 1620 (athn_clock_rate(sc) * 1000); 1621 } else 1622 listen_time = 0; 1623 1624 ani->cyccnt = cyccnt; 1625 ani->txfcnt = txfcnt; 1626 ani->rxfcnt = rxfcnt; 1627 1628 if (listen_time < 0) { 1629 athn_ani_restart(sc); 1630 return; 1631 } 1632 ani->listen_time += listen_time; 1633 1634 phy1 = AR_READ(sc, AR_PHY_ERR_1); 1635 phy2 = AR_READ(sc, AR_PHY_ERR_2); 1636 1637 if (phy1 < ani->ofdm_phy_err_base) { 1638 AR_WRITE(sc, AR_PHY_ERR_1, ani->ofdm_phy_err_base); 1639 AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 1640 } 1641 if (phy2 < ani->cck_phy_err_base) { 1642 AR_WRITE(sc, AR_PHY_ERR_2, ani->cck_phy_err_base); 1643 AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 1644 } 1645 if (phy1 < ani->ofdm_phy_err_base || phy2 < ani->cck_phy_err_base) { 1646 AR_WRITE_BARRIER(sc); 1647 return; 1648 } 1649 ani->ofdm_phy_err_count = phy1 - ani->ofdm_phy_err_base; 1650 ani->cck_phy_err_count = phy2 - ani->cck_phy_err_base; 1651 1652 if (ani->listen_time > 5 * ATHN_ANI_PERIOD) { 1653 /* Check to see if we need to lower immunity. */ 1654 if (ani->ofdm_phy_err_count <= 1655 ani->listen_time * ani->ofdm_trig_low / 1000 && 1656 ani->cck_phy_err_count <= 1657 ani->listen_time * ani->cck_trig_low / 1000) 1658 athn_ani_lower_immunity(sc); 1659 athn_ani_restart(sc); 1660 1661 } else if (ani->listen_time > ATHN_ANI_PERIOD) { 1662 /* Check to see if we need to raise immunity. */ 1663 if (ani->ofdm_phy_err_count > 1664 ani->listen_time * ani->ofdm_trig_high / 1000) { 1665 athn_ani_ofdm_err_trigger(sc); 1666 athn_ani_restart(sc); 1667 } else if (ani->cck_phy_err_count > 1668 ani->listen_time * ani->cck_trig_high / 1000) { 1669 athn_ani_cck_err_trigger(sc); 1670 athn_ani_restart(sc); 1671 } 1672 } 1673 } 1674 #endif /* notyet */ 1675 1676 PUBLIC uint8_t 1677 athn_chan2fbin(struct ieee80211_channel *c) 1678 { 1679 1680 if (IEEE80211_IS_CHAN_2GHZ(c)) 1681 return c->ic_freq - 2300; 1682 else 1683 return (c->ic_freq - 4800) / 5; 1684 } 1685 1686 PUBLIC int 1687 athn_interpolate(int x, int x1, int y1, int x2, int y2) 1688 { 1689 1690 if (x1 == x2) /* Prevents division by zero. */ 1691 return y1; 1692 /* Linear interpolation. */ 1693 return y1 + ((x - x1) * (y2 - y1)) / (x2 - x1); 1694 } 1695 1696 PUBLIC void 1697 athn_get_pier_ival(uint8_t fbin, const uint8_t *pierfreq, int npiers, 1698 int *lo, int *hi) 1699 { 1700 int i; 1701 1702 for (i = 0; i < npiers; i++) 1703 if (pierfreq[i] == AR_BCHAN_UNUSED || 1704 pierfreq[i] > fbin) 1705 break; 1706 *hi = i; 1707 *lo = *hi - 1; 1708 if (*lo == -1) 1709 *lo = *hi; 1710 else if (*hi == npiers || pierfreq[*hi] == AR_BCHAN_UNUSED) 1711 *hi = *lo; 1712 } 1713 1714 Static void 1715 athn_init_dma(struct athn_softc *sc) 1716 { 1717 uint32_t reg; 1718 1719 if (!AR_SREV_9380_10_OR_LATER(sc)) { 1720 /* Set AHB not to do cacheline prefetches. */ 1721 AR_SETBITS(sc, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); 1722 } 1723 reg = AR_READ(sc, AR_TXCFG); 1724 /* Let MAC DMA reads be in 128-byte chunks. */ 1725 reg = RW(reg, AR_TXCFG_DMASZ, AR_DMASZ_128B); 1726 1727 /* Set initial Tx trigger level. */ 1728 if (AR_SREV_9285(sc) || AR_SREV_9271(sc)) 1729 reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_256B); 1730 else if (!AR_SREV_9380_10_OR_LATER(sc)) 1731 reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_512B); 1732 AR_WRITE(sc, AR_TXCFG, reg); 1733 1734 /* Let MAC DMA writes be in 128-byte chunks. */ 1735 reg = AR_READ(sc, AR_RXCFG); 1736 reg = RW(reg, AR_RXCFG_DMASZ, AR_DMASZ_128B); 1737 AR_WRITE(sc, AR_RXCFG, reg); 1738 1739 /* Setup Rx FIFO threshold to hold off Tx activities. */ 1740 AR_WRITE(sc, AR_RXFIFO_CFG, 512); 1741 1742 /* Reduce the number of entries in PCU TXBUF to avoid wrap around. */ 1743 if (AR_SREV_9285(sc)) { 1744 AR_WRITE(sc, AR_PCU_TXBUF_CTRL, 1745 AR9285_PCU_TXBUF_CTRL_USABLE_SIZE); 1746 } else if (!AR_SREV_9271(sc)) { 1747 AR_WRITE(sc, AR_PCU_TXBUF_CTRL, 1748 AR_PCU_TXBUF_CTRL_USABLE_SIZE); 1749 } 1750 AR_WRITE_BARRIER(sc); 1751 1752 /* Reset Tx status ring. */ 1753 if (AR_SREV_9380_10_OR_LATER(sc)) 1754 ar9003_reset_txsring(sc); 1755 } 1756 1757 PUBLIC void 1758 athn_inc_tx_trigger_level(struct athn_softc *sc) 1759 { 1760 uint32_t reg, ftrig; 1761 1762 reg = AR_READ(sc, AR_TXCFG); 1763 ftrig = MS(reg, AR_TXCFG_FTRIG); 1764 /* 1765 * NB: The AR9285 and all single-stream parts have an issue that 1766 * limits the size of the PCU Tx FIFO to 2KB instead of 4KB. 1767 */ 1768 if (ftrig == ((AR_SREV_9285(sc) || AR_SREV_9271(sc)) ? 0x1f : 0x3f)) 1769 return; /* Already at max. */ 1770 reg = RW(reg, AR_TXCFG_FTRIG, ftrig + 1); 1771 AR_WRITE(sc, AR_TXCFG, reg); 1772 AR_WRITE_BARRIER(sc); 1773 } 1774 1775 PUBLIC int 1776 athn_stop_rx_dma(struct athn_softc *sc) 1777 { 1778 int ntries; 1779 1780 AR_WRITE(sc, AR_CR, AR_CR_RXD); 1781 /* Wait for Rx enable bit to go low. */ 1782 for (ntries = 0; ntries < 100; ntries++) { 1783 if (!(AR_READ(sc, AR_CR) & AR_CR_RXE)) 1784 return 0; 1785 DELAY(100); 1786 } 1787 DPRINTFN(DBG_RX, sc, "Rx DMA failed to stop\n"); 1788 return ETIMEDOUT; 1789 } 1790 1791 #ifdef unused 1792 Static int 1793 athn_rx_abort(struct athn_softc *sc) 1794 { 1795 int ntries; 1796 1797 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 1798 for (ntries = 0; ntries < 1000; ntries++) { 1799 if (MS(AR_READ(sc, AR_OBS_BUS_1), AR_OBS_BUS_1_RX_STATE) == 0) 1800 return 0; 1801 DELAY(10); 1802 } 1803 DPRINTFN(DBG_RX, sc, "Rx failed to go idle in 10ms\n"); 1804 AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 1805 AR_WRITE_BARRIER(sc); 1806 return ETIMEDOUT; 1807 } 1808 #endif /* unused */ 1809 1810 Static void 1811 athn_tx_reclaim(struct athn_softc *sc, int qid) 1812 { 1813 struct athn_txq *txq = &sc->sc_txq[qid]; 1814 struct athn_tx_buf *bf; 1815 1816 /* Reclaim all buffers queued in the specified Tx queue. */ 1817 /* NB: Tx DMA must be stopped. */ 1818 while ((bf = SIMPLEQ_FIRST(&txq->head)) != NULL) { 1819 SIMPLEQ_REMOVE_HEAD(&txq->head, bf_list); 1820 1821 bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, 1822 bf->bf_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1823 bus_dmamap_unload(sc->sc_dmat, bf->bf_map); 1824 m_freem(bf->bf_m); 1825 bf->bf_m = NULL; 1826 bf->bf_ni = NULL; /* Nodes already freed! */ 1827 1828 /* Link Tx buffer back to global free list. */ 1829 SIMPLEQ_INSERT_TAIL(&sc->sc_txbufs, bf, bf_list); 1830 } 1831 } 1832 1833 PUBLIC int 1834 athn_tx_pending(struct athn_softc *sc, int qid) 1835 { 1836 1837 return MS(AR_READ(sc, AR_QSTS(qid)), AR_Q_STS_PEND_FR_CNT) != 0 || 1838 (AR_READ(sc, AR_Q_TXE) & (1 << qid)) != 0; 1839 } 1840 1841 PUBLIC void 1842 athn_stop_tx_dma(struct athn_softc *sc, int qid) 1843 { 1844 uint32_t tsflo; 1845 int ntries, i; 1846 1847 AR_WRITE(sc, AR_Q_TXD, 1 << qid); 1848 for (ntries = 0; ntries < 40; ntries++) { 1849 if (!athn_tx_pending(sc, qid)) 1850 break; 1851 DELAY(100); 1852 } 1853 if (ntries == 40) { 1854 for (i = 0; i < 2; i++) { 1855 tsflo = AR_READ(sc, AR_TSF_L32) / 1024; 1856 AR_WRITE(sc, AR_QUIET2, 1857 SM(AR_QUIET2_QUIET_DUR, 10)); 1858 AR_WRITE(sc, AR_QUIET_PERIOD, 100); 1859 AR_WRITE(sc, AR_NEXT_QUIET_TIMER, tsflo); 1860 AR_SETBITS(sc, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 1861 if (AR_READ(sc, AR_TSF_L32) / 1024 == tsflo) 1862 break; 1863 } 1864 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 1865 AR_WRITE_BARRIER(sc); 1866 DELAY(200); 1867 AR_CLRBITS(sc, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 1868 AR_WRITE_BARRIER(sc); 1869 1870 for (ntries = 0; ntries < 40; ntries++) { 1871 if (!athn_tx_pending(sc, qid)) 1872 break; 1873 DELAY(100); 1874 } 1875 1876 AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 1877 } 1878 AR_WRITE(sc, AR_Q_TXD, 0); 1879 AR_WRITE_BARRIER(sc); 1880 } 1881 1882 PUBLIC int 1883 athn_txtime(struct athn_softc *sc, int len, int ridx, u_int flags) 1884 { 1885 #define divround(a, b) (((a) + (b) - 1) / (b)) 1886 int txtime; 1887 1888 /* XXX HT. */ 1889 if (athn_rates[ridx].phy == IEEE80211_T_OFDM) { 1890 txtime = divround(8 + 4 * len + 3, athn_rates[ridx].rate); 1891 /* SIFS is 10us for 11g but Signal Extension adds 6us. */ 1892 txtime = 16 + 4 + 4 * txtime + 16; 1893 } else { 1894 txtime = divround(16 * len, athn_rates[ridx].rate); 1895 if (ridx != ATHN_RIDX_CCK1 && (flags & IEEE80211_F_SHPREAMBLE)) 1896 txtime += 72 + 24; 1897 else 1898 txtime += 144 + 48; 1899 txtime += 10; /* 10us SIFS. */ 1900 } 1901 return txtime; 1902 #undef divround 1903 } 1904 1905 PUBLIC void 1906 athn_init_tx_queues(struct athn_softc *sc) 1907 { 1908 int qid; 1909 1910 for (qid = 0; qid < ATHN_QID_COUNT; qid++) { 1911 SIMPLEQ_INIT(&sc->sc_txq[qid].head); 1912 sc->sc_txq[qid].lastds = NULL; 1913 sc->sc_txq[qid].wait = NULL; 1914 sc->sc_txq[qid].queued = 0; 1915 1916 AR_WRITE(sc, AR_DRETRY_LIMIT(qid), 1917 SM(AR_D_RETRY_LIMIT_STA_SH, 32) | 1918 SM(AR_D_RETRY_LIMIT_STA_LG, 32) | 1919 SM(AR_D_RETRY_LIMIT_FR_SH, 10)); 1920 AR_WRITE(sc, AR_QMISC(qid), 1921 AR_Q_MISC_DCU_EARLY_TERM_REQ); 1922 AR_WRITE(sc, AR_DMISC(qid), 1923 SM(AR_D_MISC_BKOFF_THRESH, 2) | 1924 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN); 1925 } 1926 1927 /* Init beacon queue. */ 1928 AR_SETBITS(sc, AR_QMISC(ATHN_QID_BEACON), 1929 AR_Q_MISC_FSP_DBA_GATED | AR_Q_MISC_BEACON_USE | 1930 AR_Q_MISC_CBR_INCR_DIS1); 1931 AR_SETBITS(sc, AR_DMISC(ATHN_QID_BEACON), 1932 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL, 1933 AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL) | 1934 AR_D_MISC_BEACON_USE | 1935 AR_D_MISC_POST_FR_BKOFF_DIS); 1936 AR_WRITE(sc, AR_DLCL_IFS(ATHN_QID_BEACON), 1937 SM(AR_D_LCL_IFS_CWMIN, 0) | 1938 SM(AR_D_LCL_IFS_CWMAX, 0) | 1939 SM(AR_D_LCL_IFS_AIFS, 1)); 1940 1941 /* Init CAB (Content After Beacon) queue. */ 1942 AR_SETBITS(sc, AR_QMISC(ATHN_QID_CAB), 1943 AR_Q_MISC_FSP_DBA_GATED | AR_Q_MISC_CBR_INCR_DIS1 | 1944 AR_Q_MISC_CBR_INCR_DIS0); 1945 AR_SETBITS(sc, AR_DMISC(ATHN_QID_CAB), 1946 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL, 1947 AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL)); 1948 1949 /* Init PS-Poll queue. */ 1950 AR_SETBITS(sc, AR_QMISC(ATHN_QID_PSPOLL), 1951 AR_Q_MISC_CBR_INCR_DIS1); 1952 1953 /* Init UAPSD queue. */ 1954 AR_SETBITS(sc, AR_DMISC(ATHN_QID_UAPSD), 1955 AR_D_MISC_POST_FR_BKOFF_DIS); 1956 1957 if (AR_SREV_9380_10_OR_LATER(sc)) { 1958 /* Enable MAC descriptor CRC check. */ 1959 AR_WRITE(sc, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN); 1960 } 1961 /* Enable DESC interrupts for all Tx queues. */ 1962 AR_WRITE(sc, AR_IMR_S0, 0x00ff0000); 1963 /* Enable EOL interrupts for all Tx queues except UAPSD. */ 1964 AR_WRITE(sc, AR_IMR_S1, 0x00df0000); 1965 AR_WRITE_BARRIER(sc); 1966 } 1967 1968 PUBLIC void 1969 athn_set_sta_timers(struct athn_softc *sc) 1970 { 1971 struct ieee80211com *ic = &sc->sc_ic; 1972 uint32_t tsfhi, tsflo, tsftu, reg; 1973 uint32_t intval, next_tbtt, next_dtim; 1974 int dtim_period, rem_dtim_count; 1975 1976 tsfhi = AR_READ(sc, AR_TSF_U32); 1977 tsflo = AR_READ(sc, AR_TSF_L32); 1978 tsftu = AR_TSF_TO_TU(tsfhi, tsflo) + AR_FUDGE; 1979 1980 /* Beacon interval in TU. */ 1981 intval = ic->ic_bss->ni_intval; 1982 1983 next_tbtt = roundup(tsftu, intval); 1984 #ifdef notyet 1985 dtim_period = ic->ic_dtim_period; 1986 if (dtim_period <= 0) 1987 #endif 1988 dtim_period = 1; /* Assume all TIMs are DTIMs. */ 1989 1990 #ifdef notyet 1991 int dtim_count = ic->ic_dtim_count; 1992 if (dtim_count >= dtim_period) /* Should not happen. */ 1993 dtim_count = 0; /* Assume last TIM was a DTIM. */ 1994 #endif 1995 1996 /* Compute number of remaining TIMs until next DTIM. */ 1997 rem_dtim_count = 0; /* XXX */ 1998 next_dtim = next_tbtt + rem_dtim_count * intval; 1999 2000 AR_WRITE(sc, AR_NEXT_TBTT_TIMER, next_tbtt * IEEE80211_DUR_TU); 2001 AR_WRITE(sc, AR_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 2002 AR_WRITE(sc, AR_DMA_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 2003 2004 /* 2005 * Set the number of consecutive beacons to miss before raising 2006 * a BMISS interrupt to 10. 2007 */ 2008 reg = AR_READ(sc, AR_RSSI_THR); 2009 reg = RW(reg, AR_RSSI_THR_BM_THR, 10); 2010 AR_WRITE(sc, AR_RSSI_THR, reg); 2011 2012 AR_WRITE(sc, AR_NEXT_DTIM, 2013 (next_dtim - AR_SLEEP_SLOP) * IEEE80211_DUR_TU); 2014 AR_WRITE(sc, AR_NEXT_TIM, 2015 (next_tbtt - AR_SLEEP_SLOP) * IEEE80211_DUR_TU); 2016 2017 /* CAB timeout is in 1/8 TU. */ 2018 AR_WRITE(sc, AR_SLEEP1, 2019 SM(AR_SLEEP1_CAB_TIMEOUT, AR_CAB_TIMEOUT_VAL * 8) | 2020 AR_SLEEP1_ASSUME_DTIM); 2021 AR_WRITE(sc, AR_SLEEP2, 2022 SM(AR_SLEEP2_BEACON_TIMEOUT, AR_MIN_BEACON_TIMEOUT_VAL)); 2023 2024 AR_WRITE(sc, AR_TIM_PERIOD, intval * IEEE80211_DUR_TU); 2025 AR_WRITE(sc, AR_DTIM_PERIOD, dtim_period * intval * IEEE80211_DUR_TU); 2026 2027 AR_SETBITS(sc, AR_TIMER_MODE, 2028 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | AR_DTIM_TIMER_EN); 2029 2030 /* Set TSF out-of-range threshold (fixed at 16k us). */ 2031 AR_WRITE(sc, AR_TSFOOR_THRESHOLD, 0x4240); 2032 2033 AR_WRITE_BARRIER(sc); 2034 } 2035 2036 #ifndef IEEE80211_STA_ONLY 2037 PUBLIC void 2038 athn_set_hostap_timers(struct athn_softc *sc) 2039 { 2040 struct ieee80211com *ic = &sc->sc_ic; 2041 uint32_t intval, next_tbtt; 2042 2043 /* Beacon interval in TU. */ 2044 intval = ic->ic_bss->ni_intval; 2045 next_tbtt = intval; 2046 2047 AR_WRITE(sc, AR_NEXT_TBTT_TIMER, next_tbtt * IEEE80211_DUR_TU); 2048 AR_WRITE(sc, AR_NEXT_DMA_BEACON_ALERT, 2049 (next_tbtt - AR_BEACON_DMA_DELAY) * IEEE80211_DUR_TU); 2050 AR_WRITE(sc, AR_NEXT_CFP, 2051 (next_tbtt - AR_SWBA_DELAY) * IEEE80211_DUR_TU); 2052 2053 AR_WRITE(sc, AR_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 2054 AR_WRITE(sc, AR_DMA_BEACON_PERIOD, intval * IEEE80211_DUR_TU); 2055 AR_WRITE(sc, AR_SWBA_PERIOD, intval * IEEE80211_DUR_TU); 2056 AR_WRITE(sc, AR_NDP_PERIOD, intval * IEEE80211_DUR_TU); 2057 2058 AR_WRITE(sc, AR_TIMER_MODE, 2059 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN); 2060 2061 AR_WRITE_BARRIER(sc); 2062 } 2063 #endif 2064 2065 PUBLIC void 2066 athn_set_opmode(struct athn_softc *sc) 2067 { 2068 uint32_t reg; 2069 2070 switch (sc->sc_ic.ic_opmode) { 2071 #ifndef IEEE80211_STA_ONLY 2072 case IEEE80211_M_HOSTAP: 2073 reg = AR_READ(sc, AR_STA_ID1); 2074 reg &= ~AR_STA_ID1_ADHOC; 2075 reg |= AR_STA_ID1_STA_AP | AR_STA_ID1_KSRCH_MODE; 2076 AR_WRITE(sc, AR_STA_ID1, reg); 2077 2078 AR_CLRBITS(sc, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 2079 break; 2080 case IEEE80211_M_IBSS: 2081 case IEEE80211_M_AHDEMO: 2082 reg = AR_READ(sc, AR_STA_ID1); 2083 reg &= ~AR_STA_ID1_STA_AP; 2084 reg |= AR_STA_ID1_ADHOC | AR_STA_ID1_KSRCH_MODE; 2085 AR_WRITE(sc, AR_STA_ID1, reg); 2086 2087 AR_SETBITS(sc, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 2088 break; 2089 #endif 2090 default: 2091 reg = AR_READ(sc, AR_STA_ID1); 2092 reg &= ~(AR_STA_ID1_ADHOC | AR_STA_ID1_STA_AP); 2093 reg |= AR_STA_ID1_KSRCH_MODE; 2094 AR_WRITE(sc, AR_STA_ID1, reg); 2095 break; 2096 } 2097 AR_WRITE_BARRIER(sc); 2098 } 2099 2100 PUBLIC void 2101 athn_set_bss(struct athn_softc *sc, struct ieee80211_node *ni) 2102 { 2103 const uint8_t *bssid = ni->ni_bssid; 2104 2105 AR_WRITE(sc, AR_BSS_ID0, LE_READ_4(&bssid[0])); 2106 AR_WRITE(sc, AR_BSS_ID1, LE_READ_2(&bssid[4]) | 2107 SM(AR_BSS_ID1_AID, IEEE80211_AID(ni->ni_associd))); 2108 AR_WRITE_BARRIER(sc); 2109 } 2110 2111 Static void 2112 athn_enable_interrupts(struct athn_softc *sc) 2113 { 2114 uint32_t mask2; 2115 2116 athn_disable_interrupts(sc); /* XXX */ 2117 2118 AR_WRITE(sc, AR_IMR, sc->sc_imask); 2119 2120 mask2 = AR_READ(sc, AR_IMR_S2); 2121 mask2 &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC | 2122 AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | AR_IMR_S2_TSFOOR); 2123 mask2 |= AR_IMR_S2_GTT | AR_IMR_S2_CST; 2124 AR_WRITE(sc, AR_IMR_S2, mask2); 2125 2126 AR_CLRBITS(sc, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); 2127 2128 AR_WRITE(sc, AR_IER, AR_IER_ENABLE); 2129 2130 AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ); 2131 AR_WRITE(sc, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ); 2132 2133 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->sc_isync); 2134 AR_WRITE(sc, AR_INTR_SYNC_MASK, sc->sc_isync); 2135 AR_WRITE_BARRIER(sc); 2136 } 2137 2138 Static void 2139 athn_disable_interrupts(struct athn_softc *sc) 2140 { 2141 2142 AR_WRITE(sc, AR_IER, 0); 2143 (void)AR_READ(sc, AR_IER); 2144 2145 AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, 0); 2146 (void)AR_READ(sc, AR_INTR_ASYNC_ENABLE); 2147 2148 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0); 2149 (void)AR_READ(sc, AR_INTR_SYNC_ENABLE); 2150 2151 AR_WRITE(sc, AR_IMR, 0); 2152 2153 AR_CLRBITS(sc, AR_IMR_S2, AR_IMR_S2_TIM | AR_IMR_S2_DTIM | 2154 AR_IMR_S2_DTIMSYNC | AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | 2155 AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST); 2156 2157 AR_CLRBITS(sc, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); 2158 AR_WRITE_BARRIER(sc); 2159 } 2160 2161 Static void 2162 athn_init_qos(struct athn_softc *sc) 2163 { 2164 2165 /* Initialize QoS settings. */ 2166 AR_WRITE(sc, AR_MIC_QOS_CONTROL, 0x100aa); 2167 AR_WRITE(sc, AR_MIC_QOS_SELECT, 0x3210); 2168 AR_WRITE(sc, AR_QOS_NO_ACK, 2169 SM(AR_QOS_NO_ACK_TWO_BIT, 2) | 2170 SM(AR_QOS_NO_ACK_BIT_OFF, 5) | 2171 SM(AR_QOS_NO_ACK_BYTE_OFF, 0)); 2172 AR_WRITE(sc, AR_TXOP_X, AR_TXOP_X_VAL); 2173 /* Initialize TXOP for all TIDs. */ 2174 AR_WRITE(sc, AR_TXOP_0_3, 0xffffffff); 2175 AR_WRITE(sc, AR_TXOP_4_7, 0xffffffff); 2176 AR_WRITE(sc, AR_TXOP_8_11, 0xffffffff); 2177 AR_WRITE(sc, AR_TXOP_12_15, 0xffffffff); 2178 AR_WRITE_BARRIER(sc); 2179 } 2180 2181 PUBLIC int 2182 athn_hw_reset(struct athn_softc *sc, struct ieee80211_channel *curchan, 2183 struct ieee80211_channel *extchan, int init) 2184 { 2185 struct ieee80211com *ic = &sc->sc_ic; 2186 struct athn_ops *ops = &sc->sc_ops; 2187 uint32_t reg, def_ant, sta_id1, cfg_led, tsflo, tsfhi; 2188 int i, error; 2189 2190 /* XXX not if already awake */ 2191 if ((error = athn_set_power_awake(sc)) != 0) { 2192 aprint_error_dev(sc->sc_dev, "could not wakeup chip\n"); 2193 return error; 2194 } 2195 2196 /* Preserve the antenna on a channel switch. */ 2197 if ((def_ant = AR_READ(sc, AR_DEF_ANTENNA)) == 0) 2198 def_ant = 1; 2199 /* Preserve other registers. */ 2200 sta_id1 = AR_READ(sc, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 2201 cfg_led = AR_READ(sc, AR_CFG_LED) & (AR_CFG_LED_ASSOC_CTL_M | 2202 AR_CFG_LED_MODE_SEL_M | AR_CFG_LED_BLINK_THRESH_SEL_M | 2203 AR_CFG_LED_BLINK_SLOW); 2204 2205 /* Mark PHY as inactive. */ 2206 ops->disable_phy(sc); 2207 2208 if (init && AR_SREV_9271(sc)) { 2209 AR_WRITE(sc, AR9271_RESET_POWER_DOWN_CONTROL, 2210 AR9271_RADIO_RF_RST); 2211 DELAY(50); 2212 } 2213 if (AR_SREV_9280(sc) && (sc->sc_flags & ATHN_FLAG_OLPC)) { 2214 /* Save TSF before it gets cleared. */ 2215 tsfhi = AR_READ(sc, AR_TSF_U32); 2216 tsflo = AR_READ(sc, AR_TSF_L32); 2217 2218 /* NB: RTC reset clears TSF. */ 2219 error = athn_reset_power_on(sc); 2220 } else { 2221 tsfhi = tsflo = 0; /* XXX: gcc */ 2222 error = athn_reset(sc, 0); 2223 } 2224 if (error != 0) { 2225 aprint_error_dev(sc->sc_dev, 2226 "could not reset chip (error=%d)\n", error); 2227 return error; 2228 } 2229 2230 /* XXX not if already awake */ 2231 if ((error = athn_set_power_awake(sc)) != 0) { 2232 aprint_error_dev(sc->sc_dev, "could not wakeup chip\n"); 2233 return error; 2234 } 2235 2236 athn_init_pll(sc, curchan); 2237 ops->set_rf_mode(sc, curchan); 2238 2239 if (sc->sc_flags & ATHN_FLAG_RFSILENT) { 2240 /* Check that the radio is not disabled by hardware switch. */ 2241 reg = ops->gpio_read(sc, sc->sc_rfsilent_pin); 2242 if (sc->sc_flags & ATHN_FLAG_RFSILENT_REVERSED) 2243 reg = !reg; 2244 if (!reg) { 2245 aprint_error_dev(sc->sc_dev, 2246 "radio is disabled by hardware switch\n"); 2247 return EPERM; 2248 } 2249 } 2250 if (init && AR_SREV_9271(sc)) { 2251 AR_WRITE(sc, AR9271_RESET_POWER_DOWN_CONTROL, 2252 AR9271_GATE_MAC_CTL); 2253 DELAY(50); 2254 } 2255 if (AR_SREV_9280(sc) && (sc->sc_flags & ATHN_FLAG_OLPC)) { 2256 /* Restore TSF if it got cleared. */ 2257 AR_WRITE(sc, AR_TSF_L32, tsflo); 2258 AR_WRITE(sc, AR_TSF_U32, tsfhi); 2259 } 2260 2261 if (AR_SREV_9280_10_OR_LATER(sc)) 2262 AR_SETBITS(sc, sc->sc_gpio_input_en_off, AR_GPIO_JTAG_DISABLE); 2263 2264 if (AR_SREV_9287_13_OR_LATER(sc) && !AR_SREV_9380_10_OR_LATER(sc)) 2265 ar9287_1_3_enable_async_fifo(sc); 2266 2267 /* Write init values to hardware. */ 2268 ops->hw_init(sc, curchan, extchan); 2269 2270 /* 2271 * Only >=AR9280 2.0 parts are capable of encrypting unicast 2272 * management frames using CCMP. 2273 */ 2274 if (AR_SREV_9280_20_OR_LATER(sc)) { 2275 reg = AR_READ(sc, AR_AES_MUTE_MASK1); 2276 /* Do not mask the subtype field in management frames. */ 2277 reg = RW(reg, AR_AES_MUTE_MASK1_FC0_MGMT, 0xff); 2278 reg = RW(reg, AR_AES_MUTE_MASK1_FC1_MGMT, 2279 (uint32_t)~(IEEE80211_FC1_RETRY | IEEE80211_FC1_PWR_MGT | 2280 IEEE80211_FC1_MORE_DATA)); 2281 AR_WRITE(sc, AR_AES_MUTE_MASK1, reg); 2282 } else if (AR_SREV_9160_10_OR_LATER(sc)) { 2283 /* Disable hardware crypto for management frames. */ 2284 AR_CLRBITS(sc, AR_PCU_MISC_MODE2, 2285 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 2286 AR_SETBITS(sc, AR_PCU_MISC_MODE2, 2287 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 2288 } 2289 2290 if (ic->ic_curmode != IEEE80211_MODE_11B) 2291 ops->set_delta_slope(sc, curchan, extchan); 2292 2293 ops->spur_mitigate(sc, curchan, extchan); 2294 ops->init_from_rom(sc, curchan, extchan); 2295 2296 /* XXX */ 2297 AR_WRITE(sc, AR_STA_ID0, LE_READ_4(&ic->ic_myaddr[0])); 2298 AR_WRITE(sc, AR_STA_ID1, LE_READ_2(&ic->ic_myaddr[4]) | 2299 sta_id1 | AR_STA_ID1_RTS_USE_DEF | AR_STA_ID1_CRPT_MIC_ENABLE); 2300 2301 athn_set_opmode(sc); 2302 2303 AR_WRITE(sc, AR_BSSMSKL, 0xffffffff); 2304 AR_WRITE(sc, AR_BSSMSKU, 0xffff); 2305 2306 /* Restore previous antenna. */ 2307 AR_WRITE(sc, AR_DEF_ANTENNA, def_ant); 2308 2309 AR_WRITE(sc, AR_BSS_ID0, 0); 2310 AR_WRITE(sc, AR_BSS_ID1, 0); 2311 2312 AR_WRITE(sc, AR_ISR, 0xffffffff); 2313 2314 AR_WRITE(sc, AR_RSSI_THR, SM(AR_RSSI_THR_BM_THR, 7)); 2315 2316 if ((error = ops->set_synth(sc, curchan, extchan)) != 0) { 2317 aprint_error_dev(sc->sc_dev, "could not set channel\n"); 2318 return error; 2319 } 2320 sc->sc_curchan = curchan; 2321 sc->sc_curchanext = extchan; 2322 2323 for (i = 0; i < AR_NUM_DCU; i++) 2324 AR_WRITE(sc, AR_DQCUMASK(i), 1 << i); 2325 2326 athn_init_tx_queues(sc); 2327 2328 /* Initialize interrupt mask. */ 2329 sc->sc_imask = 2330 AR_IMR_TXDESC | AR_IMR_TXEOL | 2331 AR_IMR_RXERR | AR_IMR_RXEOL | AR_IMR_RXORN | 2332 AR_IMR_RXMINTR | AR_IMR_RXINTM | 2333 AR_IMR_GENTMR | AR_IMR_BCNMISC; 2334 if (AR_SREV_9380_10_OR_LATER(sc)) 2335 sc->sc_imask |= AR_IMR_RXERR | AR_IMR_HP_RXOK; 2336 #ifndef IEEE80211_STA_ONLY 2337 if (0 && ic->ic_opmode == IEEE80211_M_HOSTAP) 2338 sc->sc_imask |= AR_IMR_MIB; 2339 #endif 2340 AR_WRITE(sc, AR_IMR, sc->sc_imask); 2341 AR_SETBITS(sc, AR_IMR_S2, AR_IMR_S2_GTT); 2342 AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff); 2343 sc->sc_isync = AR_INTR_SYNC_DEFAULT; 2344 if (sc->sc_flags & ATHN_FLAG_RFSILENT) 2345 sc->sc_isync |= AR_INTR_SYNC_GPIO_PIN(sc->sc_rfsilent_pin); 2346 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->sc_isync); 2347 AR_WRITE(sc, AR_INTR_SYNC_MASK, 0); 2348 if (AR_SREV_9380_10_OR_LATER(sc)) { 2349 AR_WRITE(sc, AR_INTR_PRIO_ASYNC_ENABLE, 0); 2350 AR_WRITE(sc, AR_INTR_PRIO_ASYNC_MASK, 0); 2351 AR_WRITE(sc, AR_INTR_PRIO_SYNC_ENABLE, 0); 2352 AR_WRITE(sc, AR_INTR_PRIO_SYNC_MASK, 0); 2353 } 2354 2355 athn_init_qos(sc); 2356 2357 AR_SETBITS(sc, AR_PCU_MISC, AR_PCU_MIC_NEW_LOC_ENA); 2358 2359 if (AR_SREV_9287_13_OR_LATER(sc) && !AR_SREV_9380_10_OR_LATER(sc)) 2360 ar9287_1_3_setup_async_fifo(sc); 2361 2362 /* Disable sequence number generation in hardware. */ 2363 AR_SETBITS(sc, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); 2364 2365 athn_init_dma(sc); 2366 2367 /* Program observation bus to see MAC interrupts. */ 2368 AR_WRITE(sc, sc->sc_obs_off, 8); 2369 2370 /* Setup Rx interrupt mitigation. */ 2371 AR_WRITE(sc, AR_RIMT, SM(AR_RIMT_FIRST, 2000) | SM(AR_RIMT_LAST, 500)); 2372 2373 ops->init_baseband(sc); 2374 2375 if ((error = athn_init_calib(sc, curchan, extchan)) != 0) { 2376 aprint_error_dev(sc->sc_dev, 2377 "could not initialize calibration\n"); 2378 return error; 2379 } 2380 2381 ops->set_rxchains(sc); 2382 2383 AR_WRITE(sc, AR_CFG_LED, cfg_led | AR_CFG_SCLK_32KHZ); 2384 2385 if (sc->sc_flags & ATHN_FLAG_USB) { 2386 if (AR_SREV_9271(sc)) 2387 AR_WRITE(sc, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 2388 else 2389 AR_WRITE(sc, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 2390 } 2391 #if BYTE_ORDER == BIG_ENDIAN 2392 else { 2393 /* Default is LE, turn on swapping for BE. */ 2394 AR_WRITE(sc, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 2395 } 2396 #endif 2397 AR_WRITE_BARRIER(sc); 2398 2399 return 0; 2400 } 2401 2402 Static struct ieee80211_node * 2403 athn_node_alloc(struct ieee80211_node_table *ntp) 2404 { 2405 2406 return malloc(sizeof(struct athn_node), M_DEVBUF, 2407 M_NOWAIT | M_ZERO); 2408 } 2409 2410 Static void 2411 athn_newassoc(struct ieee80211_node *ni, int isnew) 2412 { 2413 struct ieee80211com *ic = ni->ni_ic; 2414 struct athn_softc *sc = ic->ic_ifp->if_softc; 2415 struct athn_node *an = (void *)ni; 2416 struct ieee80211_rateset *rs = &ni->ni_rates; 2417 uint8_t rate; 2418 int ridx, i, j; 2419 2420 ieee80211_amrr_node_init(&sc->sc_amrr, &an->amn); 2421 /* Start at lowest available bit-rate, AMRR will raise. */ 2422 ni->ni_txrate = 0; 2423 2424 for (i = 0; i < rs->rs_nrates; i++) { 2425 rate = rs->rs_rates[i] & IEEE80211_RATE_VAL; 2426 2427 /* Map 802.11 rate to HW rate index. */ 2428 for (ridx = 0; ridx <= ATHN_RIDX_MAX; ridx++) 2429 if (athn_rates[ridx].rate == rate) 2430 break; 2431 an->ridx[i] = ridx; 2432 DPRINTFN(DBG_STM, sc, "rate %d index %d\n", rate, ridx); 2433 2434 /* Compute fallback rate for retries. */ 2435 an->fallback[i] = i; 2436 for (j = i - 1; j >= 0; j--) { 2437 if (athn_rates[an->ridx[j]].phy == 2438 athn_rates[an->ridx[i]].phy) { 2439 an->fallback[i] = j; 2440 break; 2441 } 2442 } 2443 DPRINTFN(DBG_STM, sc, "%d fallbacks to %d\n", 2444 i, an->fallback[i]); 2445 } 2446 } 2447 2448 Static int 2449 athn_media_change(struct ifnet *ifp) 2450 { 2451 struct athn_softc *sc = ifp->if_softc; 2452 struct ieee80211com *ic = &sc->sc_ic; 2453 uint8_t rate, ridx; 2454 int error; 2455 2456 error = ieee80211_media_change(ifp); 2457 if (error != ENETRESET) 2458 return error; 2459 2460 if (ic->ic_fixed_rate != -1) { 2461 rate = ic->ic_sup_rates[ic->ic_curmode]. 2462 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 2463 /* Map 802.11 rate to HW rate index. */ 2464 for (ridx = 0; ridx <= ATHN_RIDX_MAX; ridx++) 2465 if (athn_rates[ridx].rate == rate) 2466 break; 2467 sc->sc_fixed_ridx = ridx; 2468 } 2469 if (IS_UP_AND_RUNNING(ifp)) { 2470 athn_stop(ifp, 0); 2471 error = athn_init(ifp); 2472 } 2473 return error; 2474 } 2475 2476 Static void 2477 athn_next_scan(void *arg) 2478 { 2479 struct athn_softc *sc = arg; 2480 struct ieee80211com *ic = &sc->sc_ic; 2481 int s; 2482 2483 s = splnet(); 2484 if (ic->ic_state == IEEE80211_S_SCAN) 2485 ieee80211_next_scan(ic); 2486 splx(s); 2487 } 2488 2489 Static int 2490 athn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2491 { 2492 struct ifnet *ifp = ic->ic_ifp; 2493 struct athn_softc *sc = ifp->if_softc; 2494 uint32_t reg; 2495 int error; 2496 2497 callout_stop(&sc->sc_calib_to); 2498 2499 switch (nstate) { 2500 case IEEE80211_S_INIT: 2501 athn_set_led(sc, 0); 2502 break; 2503 case IEEE80211_S_SCAN: 2504 /* Make the LED blink while scanning. */ 2505 athn_set_led(sc, !sc->sc_led_state); 2506 error = athn_switch_chan(sc, ic->ic_curchan, NULL); 2507 if (error != 0) 2508 return error; 2509 callout_schedule(&sc->sc_scan_to, hz / 5); 2510 break; 2511 case IEEE80211_S_AUTH: 2512 athn_set_led(sc, 0); 2513 error = athn_switch_chan(sc, ic->ic_curchan, NULL); 2514 if (error != 0) 2515 return error; 2516 break; 2517 case IEEE80211_S_ASSOC: 2518 break; 2519 case IEEE80211_S_RUN: 2520 athn_set_led(sc, 1); 2521 2522 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2523 break; 2524 2525 /* Fake a join to initialize the Tx rate. */ 2526 athn_newassoc(ic->ic_bss, 1); 2527 2528 athn_set_bss(sc, ic->ic_bss); 2529 athn_disable_interrupts(sc); 2530 #ifndef IEEE80211_STA_ONLY 2531 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2532 athn_set_hostap_timers(sc); 2533 /* Enable software beacon alert interrupts. */ 2534 sc->sc_imask |= AR_IMR_SWBA; 2535 } else 2536 #endif 2537 { 2538 athn_set_sta_timers(sc); 2539 /* Enable beacon miss interrupts. */ 2540 sc->sc_imask |= AR_IMR_BMISS; 2541 2542 /* Stop receiving beacons from other BSS. */ 2543 reg = AR_READ(sc, AR_RX_FILTER); 2544 reg = (reg & ~AR_RX_FILTER_BEACON) | 2545 AR_RX_FILTER_MYBEACON; 2546 AR_WRITE(sc, AR_RX_FILTER, reg); 2547 AR_WRITE_BARRIER(sc); 2548 } 2549 athn_enable_interrupts(sc); 2550 2551 if (sc->sc_sup_calib_mask != 0) { 2552 memset(&sc->sc_calib, 0, sizeof(sc->sc_calib)); 2553 sc->sc_cur_calib_mask = sc->sc_sup_calib_mask; 2554 /* ops->do_calib(sc); */ 2555 } 2556 /* XXX Start ANI. */ 2557 2558 callout_schedule(&sc->sc_calib_to, hz / 2); 2559 break; 2560 } 2561 2562 return sc->sc_newstate(ic, nstate, arg); 2563 } 2564 2565 #ifdef notyet_edca 2566 PUBLIC void 2567 athn_updateedca(struct ieee80211com *ic) 2568 { 2569 #define ATHN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */ 2570 struct athn_softc *sc = ic->ic_ifp->if_softc; 2571 const struct ieee80211_edca_ac_params *ac; 2572 int aci, qid; 2573 2574 for (aci = 0; aci < EDCA_NUM_AC; aci++) { 2575 ac = &ic->ic_edca_ac[aci]; 2576 qid = athn_ac2qid[aci]; 2577 2578 AR_WRITE(sc, AR_DLCL_IFS(qid), 2579 SM(AR_D_LCL_IFS_CWMIN, ATHN_EXP2(ac->ac_ecwmin)) | 2580 SM(AR_D_LCL_IFS_CWMAX, ATHN_EXP2(ac->ac_ecwmax)) | 2581 SM(AR_D_LCL_IFS_AIFS, ac->ac_aifsn)); 2582 if (ac->ac_txoplimit != 0) { 2583 AR_WRITE(sc, AR_DCHNTIME(qid), 2584 SM(AR_D_CHNTIME_DUR, 2585 IEEE80211_TXOP_TO_US(ac->ac_txoplimit)) | 2586 AR_D_CHNTIME_EN); 2587 } else 2588 AR_WRITE(sc, AR_DCHNTIME(qid), 0); 2589 } 2590 AR_WRITE_BARRIER(sc); 2591 #undef ATHN_EXP2 2592 } 2593 #endif /* notyet_edca */ 2594 2595 Static int 2596 athn_clock_rate(struct athn_softc *sc) 2597 { 2598 struct ieee80211com *ic = &sc->sc_ic; 2599 int clockrate; /* MHz. */ 2600 2601 if (ic->ic_curmode == IEEE80211_MODE_11A) { 2602 if (sc->sc_flags & ATHN_FLAG_FAST_PLL_CLOCK) 2603 clockrate = AR_CLOCK_RATE_FAST_5GHZ_OFDM; 2604 else 2605 clockrate = AR_CLOCK_RATE_5GHZ_OFDM; 2606 } else if (ic->ic_curmode == IEEE80211_MODE_11B) { 2607 clockrate = AR_CLOCK_RATE_CCK; 2608 } else 2609 clockrate = AR_CLOCK_RATE_2GHZ_OFDM; 2610 #ifndef IEEE80211_NO_HT 2611 if (sc->sc_curchanext != NULL) 2612 clockrate *= 2; 2613 #endif 2614 return clockrate; 2615 } 2616 2617 PUBLIC void 2618 athn_updateslot(struct ifnet *ifp) 2619 { 2620 struct athn_softc *sc = ifp->if_softc; 2621 struct ieee80211com *ic = &sc->sc_ic; 2622 int slot; 2623 2624 slot = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2625 AR_WRITE(sc, AR_D_GBL_IFS_SLOT, slot * athn_clock_rate(sc)); 2626 AR_WRITE_BARRIER(sc); 2627 } 2628 2629 Static void 2630 athn_start(struct ifnet *ifp) 2631 { 2632 struct athn_softc *sc = ifp->if_softc; 2633 struct ieee80211com *ic = &sc->sc_ic; 2634 struct ether_header *eh; 2635 struct ieee80211_node *ni; 2636 struct mbuf *m; 2637 2638 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING 2639 || !device_is_active(sc->sc_dev)) 2640 return; 2641 2642 for (;;) { 2643 if (SIMPLEQ_EMPTY(&sc->sc_txbufs)) { 2644 ifp->if_flags |= IFF_OACTIVE; 2645 break; 2646 } 2647 /* Send pending management frames first. */ 2648 IF_DEQUEUE(&ic->ic_mgtq, m); 2649 if (m != NULL) { 2650 ni = M_GETCTX(m, struct ieee80211_node *); 2651 goto sendit; 2652 } 2653 if (ic->ic_state != IEEE80211_S_RUN) 2654 break; 2655 2656 /* Encapsulate and send data frames. */ 2657 IFQ_DEQUEUE(&ifp->if_snd, m); 2658 if (m == NULL) 2659 break; 2660 2661 if (m->m_len < (int)sizeof(*eh) && 2662 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2663 if_statinc(ifp, if_oerrors); 2664 continue; 2665 } 2666 eh = mtod(m, struct ether_header *); 2667 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2668 if (ni == NULL) { 2669 m_freem(m); 2670 if_statinc(ifp, if_oerrors); 2671 continue; 2672 } 2673 2674 bpf_mtap(ifp, m, BPF_D_OUT); 2675 2676 if ((m = ieee80211_encap(ic, m, ni)) == NULL) 2677 continue; 2678 sendit: 2679 bpf_mtap3(ic->ic_rawbpf, m, BPF_D_OUT); 2680 2681 if (sc->sc_ops.tx(sc, m, ni, 0) != 0) { 2682 ieee80211_free_node(ni); 2683 if_statinc(ifp, if_oerrors); 2684 continue; 2685 } 2686 2687 sc->sc_tx_timer = 5; 2688 ifp->if_timer = 1; 2689 } 2690 } 2691 2692 Static void 2693 athn_watchdog(struct ifnet *ifp) 2694 { 2695 struct athn_softc *sc = ifp->if_softc; 2696 2697 ifp->if_timer = 0; 2698 2699 if (sc->sc_tx_timer > 0) { 2700 if (--sc->sc_tx_timer == 0) { 2701 aprint_error_dev(sc->sc_dev, "device timeout\n"); 2702 /* see athn_init, no need to call athn_stop here */ 2703 /* athn_stop(ifp, 0); */ 2704 (void)athn_init(ifp); 2705 if_statinc(ifp, if_oerrors); 2706 return; 2707 } 2708 ifp->if_timer = 1; 2709 } 2710 ieee80211_watchdog(&sc->sc_ic); 2711 } 2712 2713 Static void 2714 athn_set_multi(struct athn_softc *sc) 2715 { 2716 struct ethercom *ec = &sc->sc_ec; 2717 struct ifnet *ifp = &ec->ec_if; 2718 struct ether_multi *enm; 2719 struct ether_multistep step; 2720 const uint8_t *addr; 2721 uint32_t val, lo, hi; 2722 uint8_t bit; 2723 2724 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 2725 lo = hi = 0xffffffff; 2726 goto done2; 2727 } 2728 lo = hi = 0; 2729 ETHER_LOCK(ec); 2730 ETHER_FIRST_MULTI(step, ec, enm); 2731 while (enm != NULL) { 2732 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) { 2733 ifp->if_flags |= IFF_ALLMULTI; 2734 lo = hi = 0xffffffff; 2735 goto done; 2736 } 2737 addr = enm->enm_addrlo; 2738 /* Calculate the XOR value of all eight 6-bit words. */ 2739 val = addr[0] | addr[1] << 8 | addr[2] << 16; 2740 bit = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2741 val = addr[3] | addr[4] << 8 | addr[5] << 16; 2742 bit ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2743 bit &= 0x3f; 2744 if (bit < 32) 2745 lo |= 1 << bit; 2746 else 2747 hi |= 1 << (bit - 32); 2748 ETHER_NEXT_MULTI(step, enm); 2749 } 2750 done: 2751 ETHER_UNLOCK(ec); 2752 done2: 2753 AR_WRITE(sc, AR_MCAST_FIL0, lo); 2754 AR_WRITE(sc, AR_MCAST_FIL1, hi); 2755 AR_WRITE_BARRIER(sc); 2756 } 2757 2758 Static int 2759 athn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2760 { 2761 struct athn_softc *sc = ifp->if_softc; 2762 struct ieee80211com *ic = &sc->sc_ic; 2763 int s, error = 0; 2764 2765 s = splnet(); 2766 2767 switch (cmd) { 2768 case SIOCSIFFLAGS: 2769 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2770 break; 2771 2772 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 2773 case IFF_UP | IFF_RUNNING: 2774 #ifdef notyet 2775 if (((ifp->if_flags ^ sc->sc_if_flags) & 2776 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 2777 /* XXX: setup multi */ 2778 #endif 2779 break; 2780 case IFF_UP: 2781 athn_init(ifp); 2782 break; 2783 2784 case IFF_RUNNING: 2785 athn_stop(ifp, 1); 2786 break; 2787 case 0: 2788 default: 2789 break; 2790 } 2791 sc->sc_if_flags = ifp->if_flags; 2792 break; 2793 2794 case SIOCADDMULTI: 2795 case SIOCDELMULTI: 2796 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2797 /* setup multicast filter, etc */ 2798 athn_set_multi(sc); 2799 error = 0; 2800 } 2801 break; 2802 2803 case SIOCS80211CHANNEL: 2804 error = ieee80211_ioctl(ic, cmd, data); 2805 if (error == ENETRESET && 2806 ic->ic_opmode == IEEE80211_M_MONITOR) { 2807 if (IS_UP_AND_RUNNING(ifp)) 2808 athn_switch_chan(sc, ic->ic_curchan, NULL); 2809 error = 0; 2810 } 2811 break; 2812 2813 default: 2814 error = ieee80211_ioctl(ic, cmd, data); 2815 } 2816 2817 if (error == ENETRESET) { 2818 error = 0; 2819 if (IS_UP_AND_RUNNING(ifp) && 2820 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) { 2821 athn_stop(ifp, 0); 2822 error = athn_init(ifp); 2823 } 2824 } 2825 2826 splx(s); 2827 return error; 2828 } 2829 2830 Static int 2831 athn_init(struct ifnet *ifp) 2832 { 2833 struct athn_softc *sc = ifp->if_softc; 2834 struct athn_ops *ops = &sc->sc_ops; 2835 struct ieee80211com *ic = &sc->sc_ic; 2836 struct ieee80211_channel *curchan, *extchan; 2837 size_t i; 2838 int error; 2839 2840 KASSERT(!cpu_intr_p()); 2841 2842 if (device_is_active(sc->sc_dev)) { 2843 athn_stop(ifp, 0); /* see athn_watchdog() */ 2844 } else { 2845 short flags = ifp->if_flags; 2846 ifp->if_flags &= ~IFF_UP; 2847 /* avoid recursion in athn_resume */ 2848 if (!pmf_device_subtree_resume(sc->sc_dev, &sc->sc_qual) || 2849 !device_is_active(sc->sc_dev)) { 2850 printf("%s: failed to power up device\n", 2851 device_xname(sc->sc_dev)); 2852 return 0; 2853 } 2854 ifp->if_flags = flags; 2855 } 2856 2857 curchan = ic->ic_curchan; 2858 extchan = NULL; 2859 2860 /* In case a new MAC address has been configured. */ 2861 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 2862 2863 #ifdef openbsd_power_management 2864 /* For CardBus, power on the socket. */ 2865 if (sc->sc_enable != NULL) { 2866 if ((error = sc->sc_enable(sc)) != 0) { 2867 aprint_error_dev(sc->sc_dev, 2868 "could not enable device\n"); 2869 goto fail; 2870 } 2871 if ((error = athn_reset_power_on(sc)) != 0) { 2872 aprint_error_dev(sc->sc_dev, 2873 "could not power on device\n"); 2874 goto fail; 2875 } 2876 } 2877 #endif 2878 if (!(sc->sc_flags & ATHN_FLAG_PCIE)) 2879 athn_config_nonpcie(sc); 2880 else 2881 athn_config_pcie(sc); 2882 2883 /* Reset HW key cache entries. */ 2884 for (i = 0; i < sc->sc_kc_entries; i++) 2885 athn_reset_key(sc, i); 2886 2887 ops->enable_antenna_diversity(sc); 2888 2889 #ifdef ATHN_BT_COEXISTENCE 2890 /* Configure bluetooth coexistence for combo chips. */ 2891 if (sc->sc_flags & ATHN_FLAG_BTCOEX) 2892 athn_btcoex_init(sc); 2893 #endif 2894 2895 /* Configure LED. */ 2896 athn_led_init(sc); 2897 2898 /* Configure hardware radio switch. */ 2899 if (sc->sc_flags & ATHN_FLAG_RFSILENT) 2900 ops->rfsilent_init(sc); 2901 2902 if ((error = athn_hw_reset(sc, curchan, extchan, 1)) != 0) { 2903 aprint_error_dev(sc->sc_dev, 2904 "unable to reset hardware; reset status %d\n", error); 2905 goto fail; 2906 } 2907 2908 /* Enable Rx. */ 2909 athn_rx_start(sc); 2910 2911 /* Enable interrupts. */ 2912 athn_enable_interrupts(sc); 2913 2914 #ifdef ATHN_BT_COEXISTENCE 2915 /* Enable bluetooth coexistence for combo chips. */ 2916 if (sc->sc_flags & ATHN_FLAG_BTCOEX) 2917 athn_btcoex_enable(sc); 2918 #endif 2919 2920 ifp->if_flags &= ~IFF_OACTIVE; 2921 ifp->if_flags |= IFF_RUNNING; 2922 2923 #ifdef notyet 2924 if (ic->ic_flags & IEEE80211_F_WEPON) { 2925 /* Configure WEP keys. */ 2926 for (i = 0; i < IEEE80211_WEP_NKID; i++) 2927 athn_set_key(ic, NULL, &ic->ic_nw_keys[i]); 2928 } 2929 #endif 2930 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2931 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2932 else 2933 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2934 2935 return 0; 2936 fail: 2937 athn_stop(ifp, 1); 2938 return error; 2939 } 2940 2941 PUBLIC void 2942 athn_stop(struct ifnet *ifp, int disable) 2943 { 2944 struct athn_softc *sc = ifp->if_softc; 2945 struct ieee80211com *ic = &sc->sc_ic; 2946 int qid; 2947 2948 ifp->if_timer = sc->sc_tx_timer = 0; 2949 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2950 2951 callout_stop(&sc->sc_scan_to); 2952 /* In case we were scanning, release the scan "lock". */ 2953 // ic->ic_scan_lock = IEEE80211_SCAN_UNLOCKED; /* XXX:??? */ 2954 2955 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2956 2957 #ifdef ATHN_BT_COEXISTENCE 2958 /* Disable bluetooth coexistence for combo chips. */ 2959 if (sc->sc_flags & ATHN_FLAG_BTCOEX) 2960 athn_btcoex_disable(sc); 2961 #endif 2962 2963 /* Disable interrupts. */ 2964 athn_disable_interrupts(sc); 2965 /* Acknowledge interrupts (avoids interrupt storms). */ 2966 AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff); 2967 AR_WRITE(sc, AR_INTR_SYNC_MASK, 0); 2968 2969 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 2970 athn_stop_tx_dma(sc, qid); 2971 /* XXX call athn_hw_reset if Tx still pending? */ 2972 for (qid = 0; qid < ATHN_QID_COUNT; qid++) 2973 athn_tx_reclaim(sc, qid); 2974 2975 /* Stop Rx. */ 2976 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 2977 AR_WRITE(sc, AR_MIBC, AR_MIBC_FMC); 2978 AR_WRITE(sc, AR_MIBC, AR_MIBC_CMC); 2979 AR_WRITE(sc, AR_FILT_OFDM, 0); 2980 AR_WRITE(sc, AR_FILT_CCK, 0); 2981 AR_WRITE_BARRIER(sc); 2982 athn_set_rxfilter(sc, 0); 2983 athn_stop_rx_dma(sc); 2984 2985 athn_reset(sc, 0); 2986 athn_init_pll(sc, NULL); 2987 athn_set_power_awake(sc); 2988 athn_reset(sc, 1); 2989 athn_init_pll(sc, NULL); 2990 2991 athn_set_power_sleep(sc); 2992 2993 #if 0 /* XXX: shouldn't the pmf stuff take care of this? */ 2994 /* For CardBus, power down the socket. */ 2995 if (disable && sc->sc_disable != NULL) 2996 sc->sc_disable(sc); 2997 #endif 2998 if (disable) 2999 pmf_device_recursive_suspend(sc->sc_dev, &sc->sc_qual); 3000 } 3001 3002 Static void 3003 athn_pmf_wlan_off(device_t self) 3004 { 3005 struct athn_softc *sc = device_private(self); 3006 struct ifnet *ifp = &sc->sc_if; 3007 3008 /* Turn the interface down. */ 3009 ifp->if_flags &= ~IFF_UP; 3010 athn_stop(ifp, 1); 3011 } 3012 3013 PUBLIC void 3014 athn_suspend(struct athn_softc *sc) 3015 { 3016 struct ifnet *ifp = &sc->sc_if; 3017 3018 if (ifp->if_flags & IFF_RUNNING) 3019 athn_stop(ifp, 1); 3020 } 3021 3022 PUBLIC bool 3023 athn_resume(struct athn_softc *sc) 3024 { 3025 struct ifnet *ifp = &sc->sc_if; 3026 3027 if (ifp->if_flags & IFF_UP) 3028 athn_init(ifp); 3029 3030 return true; 3031 } 3032
Indexes created Sun Sep 21 18:09:52 GMT 2025