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    Searched refs:b101 (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/arch/riscv/include/
insn.h 465 #define LOAD_LHU 0b101
504 #define OP_SRX 0b101 // (3) (4) srl sra srlw sraw
529 #define OP_DIVU 0b101 // divu divuw
569 #define BRANCH_BGE 0b101
578 #define SYSTEM_CSRRWI 0b101
661 #define Q0_FSD_SQ 0b101 /* RV32/RV64 FSD, RV128 SQ */
671 #define Q1_J 0b101
687 #define Q1MORE_ADDW 0b101 /* RV64/RV128 */
695 #define Q2_FSDSP_SQSP 0b101 /* RV32/RV64 FSDSP, RV128 SQSP */
  /src/lib/libnvmm/
libnvmm_x86.c 1695 [0b101] = {
1778 [0b101] = {
1818 [0b101] = NVMM_X64_GPR_RDI, /* DI */
2175 if (instr->regmodrm.mod == 0b00 && base == 0b101) {
2254 instr->regmodrm.rm == 0b101);
2263 instr->regmodrm.rm == 0b101);
  /src/sys/arch/m68k/060sp/dist/
pfpsp.sa 1012 dc.l $00001229,$0000b101,$6a10f23c,$44008000
1018 dc.l $00001229,$0000b101,$6ae260d0,$02000030
1122 dc.l $ff661028,$00001229,$0000b101,$6a10f23c
1125 dc.l $00001228,$0000b101,$6a16f229,$d0800000
1260 dc.l $ff846000,$fee61028,$00001229,$0000b101
1262 dc.l $4e751028,$00001229,$0000b101,$6b00ff7c
1412 dc.l $60ffffff,$d3cc1028,$00001229,$0000b101
fpsp.sa 1782 dc.l $00001029,$0000b101,$02010080,$1d41ff65
1988 dc.l $00001229,$0000b101,$6a10f23c,$44008000
1994 dc.l $00001229,$0000b101,$6ae260d0,$02000030
2098 dc.l $ff661028,$00001229,$0000b101,$6a10f23c
2101 dc.l $00001228,$0000b101,$6a16f229,$d0800000
2236 dc.l $ff846000,$fee61028,$00001229,$0000b101
2238 dc.l $4e751028,$00001229,$0000b101,$6b00ff7c
2388 dc.l $60ff0000,$09761028,$00001229,$0000b101
fplsp.sa 1947 dc.l $60ffffff,$fc8e1228,$00001029,$0000b101

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