| /src/sys/external/bsd/compiler_rt/dist/lib/builtins/arm/ |
| sync_fetch_and_nand_8.S | 19 bic rD_LO, rN_LO, rM_LO ; \
20 bic rD_HI, rN_HI, rM_HI
|
| sync_fetch_and_nand_4.S | 17 #define nand_4(rD, rN, rM) bic rD, rN, rM
|
| bswapdi2.S | 33 bic r2, r2, #0xff0000
38 bic r0, r0, #0xff0000
|
| bswapsi2.S | 32 bic r1, r1, #0xff0000
|
| /src/lib/csu/arch/arm/ |
| crt0.S | 47 bic sp, sp, #7
|
| /src/sys/arch/arm/arm32/ |
| setstack.S | 64 bic r2, r3, #(PSR_MODE)
84 bic r2, r3, #(PSR_MODE)
|
| setcpsr.S | 54 * r0 - bic mask
60 bic r2, r3, r0
|
| /src/lib/csu/arch/earm/ |
| crt0.S | 48 bic sp, sp, #7
|
| /src/sys/arch/zaurus/zaurus/ |
| kloader_zaurus.S | 59 bic sp, sp, #0xff000000 /* clear upper 8 bits */
64 bic r8, r8, #0xff000000 /* clear upper 8 bits */
68 bic r2, r2, #CPU_CONTROL_MMU_ENABLE
69 bic r2, r2, #CPU_CONTROL_DC_ENABLE
70 bic r2, r2, #CPU_CONTROL_IC_ENABLE
86 bic r3, r3, #0xff000000
89 bic r5, r5, #0xff000000
91 bic r6, r6, #0xff000000
|
| /src/sys/arch/dreamcast/dev/microcode/ |
| aica_arm_locore.S | 46 bic r0,r0,#0x80 /* disable IRQ */
47 bic r0,r0,#0x40 /* disable FIQ */
51 bic r0,r0,#0x0004 /* DC disable */
84 bic r2,r2,#3
|
| /src/sys/arch/hpcarm/hpcarm/ |
| kloader_pxa2x0.S | 33 bic reg, reg, #0xff000000 /* clear upper 8 bits */ ;\
55 bic r2, r2, #CPU_CONTROL_MMU_ENABLE
56 bic r2, r2, #CPU_CONTROL_DC_ENABLE
57 bic r2, r2, #CPU_CONTROL_IC_ENABLE
|
| /src/sys/stand/efiboot/bootaa64/ |
| cache.S | 67 bic x0, x0, x4 /* Clear the low bit of the address */
117 bic x0, x0, #SCTLR_M
118 bic x0, x0, #SCTLR_C
125 bic x0, x0, #SCTLR_M
126 bic x0, x0, #SCTLR_C
|
| /src/external/lgpl3/gmp/dist/mpn/arm/v7a/cora15/ |
| cnd_aors_n.asm | 97 bic r7, r7, cnd
101 bic r6, r6, cnd
102 bic r7, r7, cnd
108 bic r6, r6, cnd
109 bic r7, r7, cnd
116 bic r7, r7, cnd
123 bic r6, r6, cnd
124 bic r7, r7, cnd
129 bic r6, r6, cnd
130 bic r7, r7, cn
[all...] |
| /src/sys/arch/arm/arm/ |
| cpufunc_asm_arm11.S | 100 bic r0, r0, #0xff
101 bic r0, r0, #0xf00 /* Always KERNEL_PID, i.e. 0 */
123 bic r0, r0, #0xff
124 bic r0, r0, #0xf00 /* Always KERNEL_PID, i.e. 0 */
145 bic r0, r0, #0xff
146 bic r0, r0, #0xf00 /* Always KERNEL_PID, i.e. 0 */
|
| /src/common/lib/libc/arch/alpha/string/ |
| bzero.S | 34 bic a1,63,t3 /* t3 is # bytes to do 64 bytes at a time */
52 bic t2,t0,t2 /* zero those bytes in word */
64 bic a1,63,t3 /* recalc t3 (# bytes to do 64 bytes at a
|
| /src/sys/arch/evbarm/adi_brh/ |
| brh_start.S | 66 bic r8, r8, #0xff000000 /* clear upper 8 bits */
70 bic r2, r2, #CPU_CONTROL_MMU_ENABLE
141 bic r3, r3, #(BECC_REG_BASE)
146 bic r3, r3, #(BRH_UART1_BASE)
151 bic r3, r3, #(BRH_UART2_BASE)
156 bic r3, r3, #(BRH_LED_BASE)
|
| /src/lib/libc/arch/arm/hardfloat/ |
| fpsetmask.S | 52 bic r1, r1, #VFP_FPSCR_ESUM
|
| fpsetsticky.S | 51 bic r2, r0, #VFP_FPSCR_CSUM
|
| /src/sys/arch/arm/iomd/ |
| iomd_io_asm.S | 52 bic r0, r0, #0xff000000
53 bic r0, r0, #0x00ff0000
|
| /src/sys/arch/sparc/sparc/ |
| intreg.h | 157 #define icr_si_bic(bic) do { \
158 *((uint32_t *)ICR_SI_CLR) = (bic); \
|
| /src/sys/arch/evbarm/hdl_g/ |
| hdlg_start.S | 56 bic r8, r8, #0xff000000 /* clear upper 8 bits */
60 bic r2, r2, #CPU_CONTROL_MMU_ENABLE
74 bic r0, r0, #0xff000000
76 bic r2, r2, #0xff000000
101 bic r0, r0, #0xff000000
|
| /src/sys/arch/evbarm/ixm1200/ |
| ixm1200_start.S | 63 bic r0, r0, #CPU_CONTROL_MMU_ENABLE
64 bic r0, r0, #CPU_CONTROL_AFLT_ENABLE
67 bic r0, r0, #CPU_CONTROL_BEND_ENABLE
69 bic r0, r0, #CPU_CONTROL_ROM_ENABLE
71 bic r0, r0, #CPU_CONTROL_VECRELOC
|
| /src/external/lgpl3/gmp/dist/mpn/arm/ |
| cnd_aors_n.asm | 83 bic r4, r4, cnd
84 bic r5, r5, cnd
85 bic r6, r6, cnd
97 bic r4, r4, cnd
98 bic r5, r5, cnd
109 bic r4, r4, cnd
118 bic r4, r4, cnd
119 bic r5, r5, cnd
120 bic r6, r6, cnd
121 bic r7, r7, cn
[all...] |
| /src/sys/arch/amd64/stand/prekern/ |
| prng.c | 63 struct btinfo_common *bic; local
67 bic = (struct btinfo_common *)(bootinfo.bi_data);
70 if (bic->type == type)
73 bic = (struct btinfo_common *)
74 ((uint8_t *)bic + bic->len);
76 return found ? bic : NULL;
|
| /src/common/lib/libc/arch/arm/gen/ |
| byte_swap_4.S | 44 bic r1, r1, #0x00FF0000 /* db.ca.db.ca -> db.0.db.ca */
|
