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    Searched refs:bitsLT (Results 1 - 25 of 25) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ValueTypes.h 265 bool bitsLT(EVT VT) const {
TargetLowering.h 3988 return VT.bitsLT(MinVT) ? MinVT : VT;
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMSelectionDAGInfo.cpp 107 else if (Src.getValueType().bitsLT(MVT::i32))
ARMISelLowering.cpp 7787 if (SrcEltTy.bitsLT(SmallestEltTy))
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
TargetLoweringBase.cpp 1117 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1582 if (EVT(DestVT).bitsLT(NewVT)) { // Value is expanded, e.g. i64 -> i16.
1645 if (VT.bitsLT(MinVT))
CodeGenPrepare.cpp 1289 if (SrcVT.bitsLT(DstVT)) return false;
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelDAGToDAG.cpp 1264 cast<VTSDNode>(N->getOperand(1))->getVT().bitsLT(MVT::i32)) {
1372 if (EltVT.bitsLT(XLenVT))
RISCVISelLowering.cpp 2040 assert(DstEltVT.bitsLT(SrcEltVT) &&
3275 if (OpVT.bitsLT(XLenVT)) {
5040 if (VT.bitsLT(XLenVT)) {
5882 IndexVT.getVectorElementType().bitsLT(XLenVT));
5891 if (IndexVT.getVectorElementType().bitsLT(XLenVT)) {
  /src/external/apache2/llvm/dist/llvm/include/llvm/Support/
MachineValueType.h 1080 bool bitsLT(MVT VT) const {
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
LegalizeTypesGeneric.cpp 225 assert(OldEltVT.bitsLT(OldVT) && "Result type smaller then element type!");
SelectionDAG.cpp 2648 if (LegalSVT.bitsLT(SVT))
4550 SVT = (SVT.bitsLT(Op.getValueType()) ? Op.getValueType() : SVT);
4819 assert(Operand.getValueType().bitsLT(VT) &&
4846 assert(Operand.getValueType().bitsLT(VT) &&
4865 assert(Operand.getValueType().bitsLT(VT) &&
4884 assert(Operand.getValueType().bitsLT(VT) &&
4922 .bitsLT(VT.getScalarType()))
5203 if (LegalSVT.bitsLT(SVT))
5331 if (LegalSVT.bitsLT(VT.getScalarType()))
6688 if (VT.bitsLT(LargestVT))
    [all...]
FastISel.cpp 395 if (IdxVT.bitsLT(PtrVT)) {
1785 if (DstVT.bitsLT(SrcVT))
LegalizeDAG.cpp 1452 MemVT.bitsLT(Node->getOperand(0).getValueType());
3012 if (NewEltVT.bitsLT(EltVT)) {
4777 assert(NewEltVT.bitsLT(EltVT) && "not handled");
4810 assert(NewEltVT.bitsLT(EltVT) && "not handled");
4856 assert(NewEltVT.bitsLT(EltVT) && "not handled");
DAGCombiner.cpp 5254 if (LdStMemVT.bitsLT(MemVT))
11137 if (SrcVT.bitsLT(VT) && VT.isVector()) {
11527 EVT MinAssertVT = AssertVT.bitsLT(BigA_AssertVT) ? AssertVT : BigA_AssertVT;
11546 if (AssertVT.bitsLT(BigA_AssertVT)) {
11826 ExtVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT()))
12026 if (N0.getOperand(0).getValueType().bitsLT(VT))
12177 if (LN0->isSimple() && LN0->getMemoryVT().bitsLT(VT)) {
14670 if (VT.bitsLT(In.getValueType()))
18454 if (ResultVT.bitsLT(VecEltVT))
18700 if (ScalarVT.bitsLT(LVT) && !TLI.isTruncateFree(LVT, ScalarVT)
    [all...]
SelectionDAGBuilder.cpp 261 ValueVT.bitsLT(PartEVT)) {
274 if (ValueVT.bitsLT(PartEVT)) {
288 if (ValueVT.bitsLT(Val.getValueType()))
299 ValueVT.bitsLT(PartEVT)) {
438 } else if (ValueVT.bitsLT(PartEVT)) {
LegalizeVectorTypes.cpp 499 if (BoolVT.bitsLT(CondVT))
2185 if (N->getValueType(0).bitsLT(
2484 if (N->getValueType(0).bitsLT(EltVT)) {
TargetLowering.cpp 3851 else if (Op0.getValueType().bitsLT(VT))
7880 if (VT.bitsLT(MVT::i32)) {
8507 if (RType.bitsLT(Overflow.getValueType()))
LegalizeIntegerTypes.cpp 4742 if (N->getOperand(i).getValueType().bitsLT(NOutVTElem))
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
R600ISelLowering.cpp 1240 if (MemVT.bitsLT(MVT::i32))
1358 ExtType != ISD::NON_EXTLOAD && MemVT.bitsLT(MVT::i32)) {
1584 if (VT.bitsLT(MVT::i32))
SIISelLowering.cpp 1655 VT.bitsLT(MemVT)) {
4858 if (NewVT.bitsLT(MVT::i32)) {
7935 if (VT.bitsLT(Op.getValueType()))
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86FastISel.cpp 3630 if (DstVT.bitsLT(SrcVT))
X86ISelLowering.cpp 2933 return VT.bitsLT(MinVT) ? MinVT : VT;
21942 if (Sign.getSimpleValueType().bitsLT(VT))
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64FastISel.cpp 4872 if (IdxVT.bitsLT(PtrVT)) {
AArch64ISelLowering.cpp 6731 if (SrcVT.bitsLT(VT))
8258 if (SrcEltTy.bitsLT(SmallestEltTy)) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsISelLowering.cpp 4013 return VT.bitsLT(MinVT) ? MinVT : VT;

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