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    Searched refs:bottom_pipe (Results 1 - 10 of 10) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/basics/
amdgpu_dc_common.c 61 if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
81 if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/
amdgpu_dcn_calcs.c 312 else if (pipe->bottom_pipe != NULL && pipe->bottom_pipe->plane_state == pipe->plane_state)
531 if (primary_pipe->bottom_pipe) {
532 ASSERT(primary_pipe->bottom_pipe != secondary_pipe);
533 secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe;
534 secondary_pipe->bottom_pipe->top_pipe = secondary_pipe;
536 primary_pipe->bottom_pipe = secondary_pipe;
920 if (pipe->bottom_pipe && pipe->bottom_pipe->plane_state == pipe->plane_state)
    [all...]
amdgpu_dce_calcs.c 2782 if (!pipe[i].stream || !pipe[i].bottom_pipe)
2858 data->src_height[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.viewport.height);
2859 data->src_width[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.viewport.width);
2861 pipe[i].bottom_pipe->plane_state->plane_size.surface_pitch);
2862 data->h_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.h_taps);
2863 data->v_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.v_taps);
2865 pipe[i].bottom_pipe->plane_res.scl_data.ratios.horz.value);
2867 pipe[i].bottom_pipe->plane_res.scl_data.ratios.vert.value);
2868 switch (pipe[i].bottom_pipe->plane_state->rotation) {
2893 if (!pipe[i].stream || pipe[i].bottom_pipe)
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
amdgpu_dc_resource.c 549 bool pri_split = pipe_ctx->bottom_pipe &&
550 pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state;
653 bool pri_split = pipe_ctx->bottom_pipe &&
654 pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state;
1179 tail_pipe = head_pipe->bottom_pipe;
1183 tail_pipe = tail_pipe->bottom_pipe;
1236 split_pipe->top_pipe->bottom_pipe = split_pipe->bottom_pipe;
1237 if (split_pipe->bottom_pipe)
1238 split_pipe->bottom_pipe->top_pipe = split_pipe->top_pipe
    [all...]
amdgpu_dc.c 1390 if (cur_pipe->bottom_pipe)
1391 cur_pipe->bottom_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
2333 if (pipe_ctx->bottom_pipe ||
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_hwseq.c 589 pipe_ctx->bottom_pipe = NULL;
1145 if (pipe->bottom_pipe != NULL) {
1147 if (!pipe->bottom_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(pipe->bottom_pipe->plane_res.hubp))
1157 if (lock && pipe->bottom_pipe != NULL)
1236 || (!old_pipe->bottom_pipe && new_pipe->bottom_pipe)
1237 || (old_pipe->bottom_pipe && !new_pipe->bottom_pipe)
1238 || (old_pipe->bottom_pipe && new_pipe->bottom_pip
    [all...]
amdgpu_dcn20_resource.c 1806 struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe;
1809 secondary_pipe->bottom_pipe = sec_bot_pipe;
1819 if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) {
1820 ASSERT(!secondary_pipe->bottom_pipe);
1821 secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe;
1822 secondary_pipe->bottom_pipe->top_pipe = secondary_pipe;
1824 primary_pipe->bottom_pipe = secondary_pipe;
2104 pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/
core_types.h 292 struct pipe_ctx *bottom_pipe; member in struct:pipe_ctx
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
amdgpu_dce110_hw_sequencer.c 1421 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
2153 if (pipe_ctx->bottom_pipe) {
2156 ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL);
2158 if (pipe_ctx->bottom_pipe->plane_state->visible) {
2499 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_hw_sequencer.c 1112 pipe_ctx->bottom_pipe = NULL;
2141 bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
2224 pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
2482 if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx)
2483 dcn10_program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
2961 (pipe_ctx->bottom_pipe != NULL);

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