| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dsc/ |
| amdgpu_rc_calc.c | 36 #define table_hash(mode, bpc, max_min) ((mode << 16) | (bpc << 8) | max_min)
42 #define TABLE_CASE(mode, bpc, max) case (table_hash(mode, BPC_##bpc, max)): \
43 table = qp_table_##mode##_##bpc##bpc_##max; \
44 table_size = sizeof(qp_table_##mode##_##bpc##bpc_##max)/sizeof(*qp_table_##mode##_##bpc##bpc_##max); \
48 void get_qp_set(qp_set qps, enum colour_mode cm, enum bits_per_comp bpc, enum max_min max_min, float bpp)
51 int sel = table_hash(mode, bpc, max_min);
180 void calc_rc_params(struct rc_params *rc, enum colour_mode cm, enum bits_per_comp bpc, float bpp, int slice_width, int slice_height, int minor_version
[all...] |
| rc_calc.h | 82 void calc_rc_params(struct rc_params *rc, enum colour_mode cm, enum bits_per_comp bpc, float bpp, int slice_width, int slice_height, int minor_version);
|
| amdgpu_dc_dsc.c | 932 uint32_t bpc = 0; local in function:dc_dsc_get_policy_for_timing
955 bpc = 8;
958 bpc = 10;
961 bpc = 12;
972 /* DP specs limits to 3 x bpc */
973 policy->max_target_bpp = 3 * bpc;
978 /* DP specs limits to 1.5 x bpc assume bpc is an even number */
979 policy->max_target_bpp = bpc * 3 / 2;
|
| amdgpu_rc_calc_dpi.c | 112 enum bits_per_comp bpc = (pps->bits_per_component == 8) ? BPC_8 : local in function:dscc_compute_dsc_parameters
135 calc_rc_params(&rc, mode, bpc, bpp, slice_width, slice_height, pps->dsc_version_minor);
|
| /src/sys/nfs/ |
| nfs_bootdhcp.c | 324 struct bootpcontext *bpc = context; local in function:bootpcheck
359 if (bootp->bp_hlen != bpc->halen) {
361 bpc->halen));
364 if (memcmp(bootp->bp_chaddr, bpc->haddr, bpc->halen)) {
368 bp_chaddr = malloc(3 * bpc->halen, M_TEMP, M_WAITOK);
369 haddr = malloc(3 * bpc->halen, M_TEMP, M_WAITOK);
372 ether_snprintf(bp_chaddr, 3 * bpc->halen,
374 ether_snprintf(haddr, 3 * bpc->halen, bpc->haddr)))
494 struct bootpcontext bpc; local in function:bootpc_call
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_connectors.c | 108 int bpc = 8; local in function:amdgpu_connector_get_monitor_bpc
116 if (connector->display_info.bpc)
117 bpc = connector->display_info.bpc;
124 if (connector->display_info.bpc)
125 bpc = connector->display_info.bpc;
133 if (connector->display_info.bpc)
134 bpc = connector->display_info.bpc;
[all...] |
| atombios_crtc.h | 54 int bpc,
|
| amdgpu_atombios_crtc.c | 324 int bpc = amdgpu_crtc->bpc; local in function:amdgpu_atombios_crtc_adjust_pll
365 switch (bpc) {
592 int bpc,
661 switch (bpc) {
692 switch (bpc) {
720 switch (bpc) {
763 amdgpu_crtc->bpc = 8;
779 amdgpu_crtc->bpc = amdgpu_connector_get_monitor_bpc(connector);
838 (amdgpu_crtc->bpc > 8)
[all...] |
| amdgpu_atombios_dp.c | 249 /* get bpc from the EDID */
250 static unsigned amdgpu_atombios_dp_convert_bpc_to_bpp(int bpc)
252 if (bpc == 0)
255 return bpc * 3;
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_evergreen_hdmi.c | 77 int bpc = 8; local in function:evergreen_hdmi_update_acr
81 bpc = radeon_crtc->bpc;
84 if (bpc > 8)
322 void dce4_hdmi_set_color_depth(struct drm_encoder *encoder, u32 offset, int bpc)
333 switch (bpc) {
339 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
340 connector->name, bpc);
345 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
351 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n"
[all...] |
| radeon_connectors.c | 131 int bpc = 8; local in function:radeon_get_monitor_bpc
139 if (connector->display_info.bpc)
140 bpc = connector->display_info.bpc;
147 if (connector->display_info.bpc)
148 bpc = connector->display_info.bpc;
156 if (connector->display_info.bpc)
157 bpc = connector->display_info.bpc;
[all...] |
| radeon_audio.h | 61 void (*set_color_depth)(struct drm_encoder *encoder, u32 offset, int bpc);
|
| radeon_audio.c | 96 u32 offset, int bpc);
654 int bpc = 8; local in function:radeon_hdmi_set_color_depth
663 bpc = radeon_crtc->bpc;
667 radeon_encoder->audio->set_color_depth(encoder, dig->afmt->offset, bpc);
|
| radeon_dp_mst.c | 373 if (radeon_connector->base.display_info.bpc)
374 radeon_crtc->bpc = radeon_connector->base.display_info.bpc;
376 radeon_crtc->bpc = 8;
|
| radeon_rs600.c | 169 int bpc = 0; local in function:avivo_program_fmt
175 bpc = radeon_get_monitor_bpc(connector);
183 if (bpc == 0)
186 switch (bpc) {
|
| radeon_atombios_crtc.c | 576 int bpc = radeon_crtc->bpc; local in function:atombios_adjust_pll
663 switch (bpc) {
838 int bpc,
906 switch (bpc) {
935 switch (bpc) {
977 radeon_crtc->bpc = 8;
995 radeon_crtc->bpc = radeon_get_monitor_bpc(connector);
1084 (radeon_crtc->bpc > 8))
1123 radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/ |
| amdgpu_dm_debugfs.c | 684 * Returns the current and maximum output bpc for the connector.
694 unsigned int bpc; local in function:output_bpc_show
716 bpc = 6;
719 bpc = 8;
722 bpc = 10;
725 bpc = 12;
728 bpc = 16;
734 seq_printf(m, "Current: %u\n", bpc);
735 seq_printf(m, "Maximum: %u\n", connector->display_info.bpc);
|
| /src/sys/external/bsd/drm2/dist/drm/ |
| drm_dp_helper.c | 418 * Returns max bpc on success or 0 if max bpc not defined
426 int bpc; local in function:drm_dp_downstream_max_bpc
436 bpc = port_cap[2] & DP_DS_MAX_BPC_MASK;
438 switch (bpc) {
484 int bpc; local in function:drm_dp_downstream_debug
547 bpc = drm_dp_downstream_max_bpc(dpcd, port_cap);
549 if (bpc > 0)
550 seq_printf(m, "\t\tMax bpc: %d\n", bpc);
[all...] |
| drm_edid.c | 86 /* Force 8bpc */
88 /* Force 12bpc */
90 /* Force 6bpc */
92 /* Force 10bpc */
120 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
123 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
126 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel *
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/nouveau/dispnv50/ |
| atom.h | 124 u8 bpc; member in struct:nv50_head_atom::__anonf635598f0d08
|
| nouveau_dispnv50_disp.c | 384 asyh->or.bpc = connector->display_info.bpc;
926 * remains the same and avoid recalculating it, as the connector's bpc
934 * the bpc to 8 to save bandwidth on the topology. In the
936 * selecting the highest possible bpc that would fit in the
939 asyh->or.bpc = min(connector->display_info.bpc, 8U);
940 asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3, false);
954 nv50_dp_bpc_to_depth(unsigned int bpc)
956 switch (bpc) {
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_dsc.c | 451 enum dsc_bits_per_comp bpc = DSC_BPC_UNKNOWN; local in function:dsc_dc_color_depth_to_dsc_bits_per_comp
455 bpc = DSC_BPC_8;
458 bpc = DSC_BPC_10;
461 bpc = DSC_BPC_12;
464 bpc = DSC_BPC_UNKNOWN;
468 return bpc;
|
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_hdmi.c | 955 /* phase information not relevant for 8bpc */
1925 * for 12bpc with pixel repeat.
1969 * The procedure for 12bpc is as follows:
1971 * 2. enable HDMI with 8bpc
1972 * 3. enable HDMI with 12bpc
2195 /* check if we can do 8bpc */
2199 /* if we can't do 8bpc we may still be able to do 12bpc */
2204 /* if we can't do 8,12bpc we may still be able to do 10bpc */
2326 int bpc; local in function:intel_hdmi_compute_bpc
2346 int bpc, clock = adjusted_mode->crtc_clock; local in function:intel_hdmi_compute_clock
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/nouveau/ |
| nouveau_connector.c | 880 if (nv_connector->edid && connector->display_info.bpc)
885 connector->display_info.bpc = 6;
889 /* we're out of options unless we're LVDS, default to 8bpc */
891 connector->display_info.bpc = 8;
895 connector->display_info.bpc = 6;
900 connector->display_info.bpc = 8;
915 connector->display_info.bpc = 8;
1081 clock = clock * (connector->display_info.bpc * 3) / 10;
|
| /src/sys/arch/hppa/dev/ |
| summitfb.c | 1582 bufsize = sizeof(struct wsdisplay_font) + 32 + fp->bpc * (fp->last - fp->first);
1602 memcpy(fontdata, font, (0x80 - fp->first) * fp->bpc);
1604 memset(fontdata + 0x80 * fp->bpc, 0, 0x20 * fp->bpc);
1607 dst = fontdata + fp->bpc * i;
1610 src = font + fp->bpc * si;
1611 memcpy(dst, src, fp->bpc);
1614 memset(dst, 0, fp->bpc);
|
