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    Searched refs:buildAShr (Results 1 - 5 of 5) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
LegalizerHelper.cpp 302 PadReg = MIRBuilder.buildAShr(GCDTy, VRegs.back(), ShiftAmt).getReg(0);
1168 MIRBuilder.buildAShr(NarrowTy, PartialExtensionReg, AshrCstReg)
1821 auto Result = IsSigned ? MIRBuilder.buildAShr(WideTy, WideInst, ShiftK)
2977 auto Shifted = MIRBuilder.buildAShr(Ty, Res, ShiftAmt);
3149 MIRBuilder.buildAShr(DstReg, TmpRes, MIBSz->getOperand(0));
3205 MIRBuilder.buildAShr(DstTy, OpReg, ShiftAmt);
4407 Hi = Lo = MIRBuilder.buildAShr(
4410 Lo = MIRBuilder.buildAShr(NVT, InH,
4412 Hi = MIRBuilder.buildAShr(NVT, InH,
4416 Hi = MIRBuilder.buildAShr(NVT, InH
    [all...]
CombinerHelper.cpp 2240 auto Hi = Builder.buildAShr(
2255 auto Lo = Builder.buildAShr(
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
MachineIRBuilder.h 1496 MachineInstrBuilder buildAShr(const DstOp &Dst, const SrcOp &Src0,
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPULegalizerInfo.cpp 2005 auto Shr = B.buildAShr(S64, FractMask, Exp);
3032 auto LHSign = B.buildAShr(Ty, LHS, SignBitOffset);
3033 auto RHSign = B.buildAShr(Ty, RHS, SignBitOffset);
AMDGPURegisterBankInfo.cpp 1616 auto ShiftHi = B.buildAShr(S32, Bitcast, B.buildConstant(S32, 16));
1890 B.buildAShr(Hi32Reg, Lo32Reg, ShiftAmt);
2395 B.buildAShr(DstRegs[1], DstRegs[0], B.buildConstant(S32, 31));

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