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    Searched refs:buildAdd (Results 1 - 6 of 6) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
LegalizerHelper.cpp 2560 auto TmpIdx = MIRBuilder.buildAdd(IdxTy, NewBaseIdx, IdxOffset);
3058 MIRBuilder.buildAdd(Res, LHS, RHS);
3072 auto TmpRes = MIRBuilder.buildAdd(Ty, LHS, RHS);
3074 MIRBuilder.buildAdd(Res, TmpRes, ZExtCarryIn);
3206 auto Add = MIRBuilder.buildAdd(DstTy, OpReg, Shift);
4710 CarrySum = B.buildAdd(NarrowTy, CarrySum, Carry).getReg(0);
4714 FactorSum = B.buildAdd(NarrowTy, Factors[0], Factors[1]).getReg(0);
4716 FactorSum = B.buildAdd(NarrowTy, FactorSum, Factors[i]).getReg(0);
5154 auto HiIsZeroCTLZ = B.buildAdd(DstTy, LoCTLZ, C_NarrowSize);
5190 auto LoIsZeroCTTZ = B.buildAdd(DstTy, HiCTTZ, C_NarrowSize)
    [all...]
CombinerHelper.cpp 3308 auto Add = Builder.buildAdd(Ty, Pow2Src1, NegOne);
IRTranslator.cpp 2603 auto AllocAdd = MIRBuilder.buildAdd(IntPtrTy, AllocSize, SAMinusOne,
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPULegalizerInfo.cpp 2815 Z = B.buildAdd(S32, Z, B.buildUMulH(S32, Z, NegYZ));
2825 Q = B.buildSelect(S32, Cond, B.buildAdd(S32, Q, One), Q);
2831 B.buildSelect(DstReg, Cond, B.buildAdd(S32, Q, One), Q);
2905 auto Add1_HiNc = B.buildAdd(S32, RcpHi, MulHi1_Hi);
2959 auto Add3 = B.buildAdd(S64, MulHi3, One64);
2969 auto Add4 = B.buildAdd(S64, Add3, One64);
3035 LHS = B.buildAdd(Ty, LHS, LHSign).getReg(0);
3036 RHS = B.buildAdd(Ty, RHS, RHSign).getReg(0);
3568 BaseReg = B.buildAdd(S32, BaseReg, OverflowVal).getReg(0);
AMDGPURegisterBankInfo.cpp 1716 BaseReg = B.buildAdd(S32, BaseReg, OverflowVal).getReg(0);
1864 auto Add = B.buildAdd(S32, WaterfallIdx, MaterializedOffset);
2665 auto IdxHi = B.buildAdd(S32, IdxLo, One);
2781 auto IdxHi = B.buildAdd(S32, IdxLo, One);
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
MachineIRBuilder.h 1396 MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0,

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