| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsCallLowering.cpp | 146 auto Lo = MIRBuilder.buildCopy(s32, Register(PhysReg + (IsEL ? 0 : 1)));
147 auto Hi = MIRBuilder.buildCopy(s32, Register(PhysReg + (IsEL ? 1 : 0)));
152 MIRBuilder.buildCopy(ValVReg, PhysReg);
159 auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg);
164 MIRBuilder.buildCopy(ValVReg, PhysReg);
248 MIRBuilder.buildCopy(Register(PhysReg + (IsEL ? 0 : 1)), Unmerge.getReg(0));
249 MIRBuilder.buildCopy(Register(PhysReg + (IsEL ? 1 : 0)), Unmerge.getReg(1));
251 MIRBuilder.buildCopy(PhysReg, ValVReg);
254 MIRBuilder.buildCopy(PhysReg, ExtReg);
266 auto SPReg = MIRBuilder.buildCopy(p0, Register(Mips::SP))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86AvoidStoreForwardingBlocks.cpp | 109 void buildCopy(MachineInstr *LoadInst, unsigned NLoadOpcode, int64_t LoadDisp,
385 void X86AvoidSFBPass::buildCopy(MachineInstr *LoadInst, unsigned NLoadOpcode,
445 buildCopy(LoadInst, getYMMtoXMMLoadOpcode(LoadInst->getOpcode()), LdDisp,
456 buildCopy(LoadInst, X86::MOV64rm, LdDisp, StoreInst, X86::MOV64mr, StDisp,
466 buildCopy(LoadInst, X86::MOV32rm, LdDisp, StoreInst, X86::MOV32mr, StDisp,
476 buildCopy(LoadInst, X86::MOV16rm, LdDisp, StoreInst, X86::MOV16mr, StDisp,
486 buildCopy(LoadInst, X86::MOV8rm, LdDisp, StoreInst, X86::MOV8mr, StDisp,
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| X86CallLowering.cpp | 97 MIRBuilder.buildCopy(p0, STI.getRegisterInfo()->getStackRegister());
111 MIRBuilder.buildCopy(PhysReg, ExtReg);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMCallLowering.cpp | 101 auto SPReg = MIRBuilder.buildCopy(p0, Register(ARM::SP));
120 MIRBuilder.buildCopy(PhysReg, ExtReg);
295 MIRBuilder.buildCopy(ValVReg, PhysReg);
302 auto PhysRegToVReg = MIRBuilder.buildCopy(LLT::scalar(LocSize), PhysReg);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUCallLowering.cpp | 78 MIRBuilder.buildCopy(PhysReg, ExtReg);
112 auto Copy = MIRBuilder.buildCopy(LLT::scalar(32), PhysReg);
201 SPReg = MIRBuilder.buildCopy(PtrTy, MFI->getStackPtrOffsetReg()).getReg(0);
214 MIRBuilder.buildCopy(PhysReg, ExtReg);
389 B.buildCopy(ReturnAddrVReg, LiveInReturn);
467 B.buildCopy(VReg, InputPtrReg);
598 B.buildCopy(LiveInReturn, ReturnAddrReg);
1091 MIRBuilder.buildCopy(LLT::vector(4, 32), FuncInfo.getScratchRSrcReg());
1092 MIRBuilder.buildCopy(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, ScratchRSrcReg);
1097 MIRBuilder.buildCopy((Register)ArgReg.first, ArgReg.second)
[all...] |
| AMDGPURegisterBankInfo.cpp | 845 OpReg = B.buildCopy(OpTy, OpReg).getReg(0);
1093 Reg = B.buildCopy(Ty, Reg).getReg(0);
1278 auto SPCopy = B.buildCopy(PtrTy, SPReg);
1406 VOffsetReg = B.buildCopy(S32, CombinedOffset).getReg(0);
1885 B.buildCopy(Hi32Reg, Lo32Reg);
1934 Idx = B.buildCopy(S32, Idx)->getOperand(0).getReg();
1970 B.buildCopy(DstReg, Res[L]);
2019 Idx = B.buildCopy(S32, Idx)->getOperand(0).getReg();
2100 auto Copy = B.buildCopy(LLT::scalar(1), SrcReg);
2389 B.buildCopy(DstRegs[0], SrcRegs[0])
[all...] |
| AMDGPULegalizerInfo.cpp | 2745 B.buildCopy(DstReg, LiveIn);
4570 B.buildCopy(SGPR01, LiveIn);
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| InlineAsmLowering.cpp | 269 MIRBuilder.buildCopy(Dst, Src);
630 MIRBuilder.buildCopy(Tmp1Reg, SrcReg);
634 MIRBuilder.buildCopy(ResRegs[i], SrcReg);
|
| CSEMIRBuilder.cpp | 147 return buildCopy(Op.getReg(), MIB.getReg(0));
|
| IRTranslator.cpp | 328 MIRBuilder.buildCopy(
331 MIRBuilder.buildCopy(
1281 MIRBuilder.buildCopy(Regs[0], VReg);
1325 MIRBuilder.buildCopy(VReg, Vals[0]);
1436 MIRBuilder.buildCopy(Regs[0], Src);
1544 MIRBuilder.buildCopy(getOrCreateVReg(U), BaseReg);
2069 MIRBuilder.buildCopy(Reg, StackPtr);
2083 MIRBuilder.buildCopy(StackPtr, Reg);
2113 MIRBuilder.buildCopy(getOrCreateVReg(CI),
2237 MIRBuilder.buildCopy(SwiftInVReg, SwiftError.getOrCreateVRegUseAt
[all...] |
| CallLowering.cpp | 705 MIRBuilder.buildCopy(Args[i].Regs[0], StackAddr);
1144 MIRBuilder.buildCopy(ValVReg, PhysReg);
1148 auto Copy = MIRBuilder.buildCopy(LocTy, PhysReg);
|
| MachineIRBuilder.cpp | 238 MachineInstrBuilder MachineIRBuilder::buildCopy(const DstOp &Res,
503 return buildCopy(Dst, Src);
|
| CombinerHelper.cpp | 128 Builder.buildCopy(ToReg, FromReg);
334 Builder.buildCopy(NewDstReg, Ops[0]);
685 Builder.buildCopy(MI.getOperand(0).getReg(), MI.getOperand(1).getReg());
2293 Builder.buildCopy(DstReg, Reg);
|
| LegalizerHelper.cpp | 871 MIRBuilder.buildCopy(MI.getOperand(0), Unmerge.getReg(0));
4940 MIRBuilder.buildCopy(DstReg, DstRegs[0]);
6307 MIRBuilder.buildCopy(DstReg, Val);
6356 auto SPTmp = MIRBuilder.buildCopy(PtrTy, SPReg);
6371 MIRBuilder.buildCopy(SPReg, SPTmp);
6372 MIRBuilder.buildCopy(Dst, SPTmp);
6773 MIRBuilder.buildCopy(ValReg, PhysReg);
6775 MIRBuilder.buildCopy(PhysReg, ValReg);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| AArch64CallLowering.cpp | 253 SPReg = MIRBuilder.buildCopy(p0, Register(AArch64::SP)).getReg(0);
276 MIRBuilder.buildCopy(PhysReg, ExtReg);
458 MIRBuilder.buildCopy(AArch64::X21, SwiftErrorVReg);
504 MIRBuilder.buildCopy(Register(F.VReg), Register(F.PReg));
1009 MIRBuilder.buildCopy(ForwardedReg, Register(F.VReg));
1147 MIRBuilder.buildCopy(Info.SwiftErrorVReg, Register(AArch64::X21));
|
| AArch64InstructionSelector.cpp | 919 auto Copy = MIB.buildCopy({DstTempRC}, {SrcReg});
1878 auto Copy = MIB.buildCopy(LLT::scalar(64), SrcOp);
1905 auto NewSrc = MIB.buildCopy(LLT::scalar(64), I.getOperand(1).getReg());
2423 MIB.buildCopy({DefReg}, {LoadMI->getOperand(0).getReg()});
2433 MIB.buildCopy({DefReg}, {DefGPRReg});
3332 MIB.buildCopy(Register(AArch64::X0), LoadGOT.getReg(0));
3341 MIB.buildCopy(I.getOperand(0).getReg(), Register(AArch64::X0));
3622 MIB.buildCopy(DstReg, Cmp.getReg(0));
4788 auto Copy = MIRBuilder.buildCopy(Dst, CPLoad->getOperand(0));
4971 MIB.buildCopy({SrcReg}, {I.getOperand(2)})
[all...] |
| AArch64PostLegalizerCombiner.cpp | 229 B.buildCopy(DstReg, Res.getReg(0));
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| SplitKit.h | 451 SlotIndex buildCopy(Register FromReg, Register ToReg, LaneBitmask LaneMask,
|
| SplitKit.cpp | 548 SlotIndex SplitEditor::buildCopy(Register FromReg, Register ToReg,
632 Def = buildCopy(Edit->getReg(), Reg, LaneMask, MBB, I, Late, RegIdx);
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| LegalizationArtifactCombiner.h | 505 Builder.buildCopy(DstReg, SrcReg);
|
| MachineIRBuilder.h | 817 MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op);
|
