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  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
MachineIRBuilder.h 375 MachineInstrBuilder buildInstr(unsigned Opcode) {
489 return buildInstr(TargetOpcode::G_PTRMASK, {Res}, {Op0, Op1});
522 return buildInstr(TargetOpcode::G_UADDO, {Res, CarryOut}, {Op0, Op1});
528 return buildInstr(TargetOpcode::G_USUBO, {Res, CarryOut}, {Op0, Op1});
534 return buildInstr(TargetOpcode::G_SADDO, {Res, CarryOut}, {Op0, Op1});
540 return buildInstr(TargetOpcode::G_SSUBO, {Res, CarryOut}, {Op0, Op1});
560 return buildInstr(TargetOpcode::G_UADDE, {Res, CarryOut},
568 return buildInstr(TargetOpcode::G_USUBE, {Res, CarryOut},
576 return buildInstr(TargetOpcode::G_SADDE, {Res, CarryOut},
584 return buildInstr(TargetOpcode::G_SSUBE, {Res, CarryOut}
    [all...]
CSEMIRBuilder.h 93 // Unhide buildInstr
94 MachineInstrBuilder buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps,
LegalizationArtifactCombiner.h 77 Builder.buildInstr(ExtMI->getOpcode(), {DstReg}, {ExtSrc});
177 Builder.buildInstr(
192 Builder.buildInstr(ExtMI->getOpcode(), {DstReg}, {ExtSrc});
335 Builder.buildInstr(TargetOpcode::G_IMPLICIT_DEF, {DstReg}, {});
662 Builder.buildInstr(ConvertOp, {DstRegs[k]}, {TmpRegs[k]});
705 Builder.buildInstr(ConvertOp, {DefReg}, {MergeSrc});
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/GISel/
PPCCallLowering.cpp 35 MIRBuilder.buildInstr(PPC::BLR8);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
MachineIRBuilder.cpp 85 return buildInstr(TargetOpcode::DBG_VALUE)
121 auto MIB = buildInstr(TargetOpcode::DBG_LABEL);
130 auto MIB = buildInstr(TargetOpcode::G_DYN_STACKALLOC);
140 auto MIB = buildInstr(TargetOpcode::G_FRAME_INDEX);
153 auto MIB = buildInstr(TargetOpcode::G_GLOBAL_VALUE);
161 return buildInstr(TargetOpcode::G_JUMP_TABLE, {PtrTy}, {})
189 return buildInstr(TargetOpcode::G_PTR_ADD, {Res}, {Op0, Op1});
219 return buildInstr(TargetOpcode::G_BR).addMBB(&Dest);
224 return buildInstr(TargetOpcode::G_BRINDIRECT).addUse(Tgt);
232 return buildInstr(TargetOpcode::G_BRJT
    [all...]
CSEMIRBuilder.cpp 167 MachineInstrBuilder CSEMIRBuilder::buildInstr(unsigned Opc,
209 return MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps, Flag);
213 auto MIB = MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps, Flag);
230 MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps, Flag);
IRTranslator.cpp 295 MIRBuilder.buildInstr(Opcode, {Res}, {Op0, Op1}, Flags);
308 MIRBuilder.buildInstr(Opcode, {Res}, {Op0}, Flags);
1455 MIRBuilder.buildInstr(Opcode, {Res}, {Op});
1574 auto ICall = MIRBuilder.buildInstr(Opcode);
1618 MIRBuilder.buildInstr(TargetOpcode::LOAD_STACK_GUARD, {DstReg}, {});
1637 MIRBuilder.buildInstr(
1650 MIRBuilder.buildInstr(Op, {Dst}, { Src0, Src1, Scale });
1766 MIRBuilder.buildInstr(Op, {getOrCreateVReg(CI)}, VRegs,
1812 MIRBuilder.buildInstr(Opcode, {getOrCreateVReg(FPI)}, VRegs, Flags);
1851 MIRBuilder.buildInstr(Op).addFrameIndex(getOrCreateFrameIndex(*AI))
    [all...]
LegalizerHelper.cpp 1045 MIRBuilder.buildInstr(TargetOpcode::G_PHI).addDef(DstRegs[i]);
1174 .buildInstr(
1199 auto DstPart = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy},
1257 auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO});
1273 MIRBuilder.buildInstr(TruncOpcode, {MO}, {DstExt});
1282 MIRBuilder.buildInstr(ExtOpcode, {MO}, {DstTrunc});
1586 auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES);
1761 auto LHSExt = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MI.getOperand(2)});
1762 auto RHSExt = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MI.getOperand(3)});
1768 .buildInstr(Opcode, {WideTy, CarryOutTy}
    [all...]
CombinerHelper.cpp 934 auto MIB = MIRBuilder.buildInstr(NewOpcode);
1038 Builder.buildInstr(IsSigned ? TargetOpcode::G_SDIVREM
1878 Builder.buildInstr(Opcode, {DestType}, {Shift1Base, Const}).getReg(0);
1882 .buildInstr(Opcode, {DestType},
1887 Builder.buildInstr(MatchInfo.Logic->getOpcode(), {Dest}, {Shift1, Shift2});
2457 Builder.buildInstr(SrcExtOp, {DstReg}, {Reg});
2520 Builder.buildInstr(SrcExtOp, {DstReg}, {SrcReg});
2962 MachineInstrBuilder Instr = Builder.buildInstr(InstrToBuild.Opcode);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64PostLegalizerLowering.cpp 399 MIRBuilder.buildInstr(MatchInfo.Opc, {MatchInfo.Dst}, MatchInfo.SrcOps);
412 MIRBuilder.buildInstr(MatchInfo.Opc, {MatchInfo.Dst},
507 MIB.buildInstr(NewOpc, {MI.getOperand(0)}, {MI.getOperand(1), ImmDef});
716 B.buildInstr(MatchInfo.first, {MI.getOperand(0).getReg()}, {DupSrc, Lane});
738 B.buildInstr(AArch64::G_DUP, {MI.getOperand(0).getReg()},
867 ? MIB.buildInstr(AArch64::G_FCMEQZ, {DstTy}, {LHS})
868 : MIB.buildInstr(AArch64::G_FCMEQ, {DstTy}, {LHS, RHS});
874 ? MIB.buildInstr(AArch64::G_FCMEQZ, {DstTy}, {LHS}).getReg(0)
875 : MIB.buildInstr(AArch64::G_FCMEQ, {DstTy}, {LHS, RHS})
881 ? MIB.buildInstr(AArch64::G_FCMGEZ, {DstTy}, {LHS}).getReg(0
    [all...]
AArch64InstructionSelector.cpp 813 MIB.buildInstr(TargetOpcode::COPY, {To}, {}).addReg(SrcReg, 0, SubReg);
1058 auto FCSel = MIB.buildInstr(Opc, {Dst}, {True, False}).addImm(CC);
1207 auto SelectInst = MIB.buildInstr(Opc, {Dst}, {True, False}).addImm(CC);
1391 MIB.buildInstr(Opc).addReg(TestReg).addImm(Bit).addMBB(DstMBB);
1453 auto BranchMI = MIB.buildInstr(Opc, {}, {CompareReg}).addMBB(DestMBB);
1470 MIB.buildInstr(AArch64::Bcc, {}, {}).addImm(CC1).addMBB(DestMBB);
1472 MIB.buildInstr(AArch64::Bcc, {}, {}).addImm(CC2).addMBB(DestMBB);
1576 MIB.buildInstr(AArch64::Bcc, {}, {}).addImm(CC).addMBB(DestMBB);
1610 MIB.buildInstr(AArch64::ANDSWri, {LLT::scalar(32)}, {CondReg}).addImm(1);
1612 auto Bcc = MIB.buildInstr(AArch64::Bcc
    [all...]
AArch64PostLegalizerCombiner.cpp 105 B.buildInstr(Opc, {MI.getOperand(0).getReg()}, {Elt0, Elt1});
216 auto Res = B.buildInstr(AddSubOpc, {Ty}, {AddSubLHS, AddSubRHS});
266 B.buildInstr(TargetOpcode::G_SBFX, {Dst}, {ShiftSrc, Cst1, Cst2});
AArch64GlobalISelUtils.cpp 90 .buildInstr(TargetOpcode::G_BZERO, {},
AArch64LegalizerInfo.cpp 869 auto ADRP = MIRBuilder.buildInstr(AArch64::ADRP, {LLT::pointer(0, 64)}, {})
890 ADRP = MIRBuilder.buildInstr(AArch64::MOVKXi, {LLT::pointer(0, 64)}, {ADRP})
897 MIRBuilder.buildInstr(AArch64::G_ADD_LOW, {DstReg}, {ADRP})
1111 MIRBuilder.buildInstr(TargetOpcode::REG_SEQUENCE, {CASDesired}, {})
1116 MIRBuilder.buildInstr(TargetOpcode::REG_SEQUENCE, {CASNew}, {})
1122 CAS = MIRBuilder.buildInstr(Opcode, {CASDst}, {CASDesired, CASNew, Addr});
1131 CAS = MIRBuilder.buildInstr(AArch64::CMP_SWAP_128, {DstLo, DstHi, Scratch},
AArch64CallLowering.cpp 413 CurVReg = MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg})
435 CurVReg = MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg})
912 CallSeqStart = MIRBuilder.buildInstr(AArch64::ADJCALLSTACKDOWN);
1023 MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP).addImm(0).addImm(0);
1084 CallSeqStart = MIRBuilder.buildInstr(AArch64::ADJCALLSTACKDOWN);
1157 MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP)
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUPostLegalizerCombiner.cpp 116 B.buildInstr(Opc, {MI.getOperand(0)}, {X, Y}, MI.getFlags());
193 B.buildInstr(AMDGPU::G_AMDGPU_CVT_F32_UBYTE0, {DstReg},
196 auto Cvt0 = B.buildInstr(AMDGPU::G_AMDGPU_CVT_F32_UBYTE0, {S32},
246 B.buildInstr(NewOpc, {MI.getOperand(0)}, {CvtSrc}, MI.getFlags());
AMDGPUPreLegalizerCombiner.cpp 135 B.buildInstr(AMDGPU::G_AMDGPU_CVT_PK_I16_I32, {V2S16},
145 auto Med3 = B.buildInstr(
AMDGPURegisterBankInfo.cpp 661 B.buildInstr(AMDGPU::G_UNMERGE_VALUES)
757 B.buildInstr(TargetOpcode::IMPLICIT_DEF)
786 B.buildInstr(TargetOpcode::PHI)
794 B.buildInstr(TargetOpcode::G_PHI)
871 B.buildInstr(AMDGPU::V_CMP_EQ_U32_e64)
881 B.buildInstr(WaveAndOpc)
965 B.buildInstr(CmpOp)
974 B.buildInstr(WaveAndOpc)
1003 B.buildInstr(AndSaveExecOpc)
1010 B.buildInstr(XorTermOpc
    [all...]
AMDGPURegBankCombiner.cpp 137 B.buildInstr(MatchInfo.Opc, {MI.getOperand(0)},
AMDGPULegalizerInfo.cpp 1757 B.buildInstr(AMDGPU::S_GETREG_B32)
2261 MachineInstrBuilder MIB = B.buildInstr(AMDGPU::SI_PC_ADD_REL_OFFSET)
2508 B.buildInstr(AMDGPU::G_AMDGPU_ATOMIC_CMPXCHG)
2807 auto RcpIFlag = B.buildInstr(AMDGPU::G_AMDGPU_RCP_IFLAG, {S32}, {FloatY});
2860 auto Rcp = B.buildInstr(AMDGPU::G_AMDGPU_RCP_IFLAG, {S32}, {Mad});
3196 B.buildInstr(AMDGPU::S_DENORM_MODE)
3205 B.buildInstr(AMDGPU::S_SETREG_IMM32_B32)
3729 auto MIB = B.buildInstr(Opc)
3832 auto MIB = B.buildInstr(Opc)
3873 B.buildInstr(Opc
    [all...]
AMDGPUCallLowering.cpp 326 Reg = B.buildInstr(ExtendOp, {ExtTy}, {Reg}).getReg(0);
363 B.buildInstr(AMDGPU::S_ENDPGM)
1123 CallSeqStart = MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKUP);
1217 MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKDOWN).addImm(NumBytes).addImm(0);
1295 MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKUP)
1377 MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKDOWN)
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86CallLowering.cpp 303 auto CallSeqStart = MIRBuilder.buildInstr(AdjStackDown);
345 MIRBuilder.buildInstr(X86::MOV8ri)
391 MIRBuilder.buildInstr(AdjStackUp)
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsLegalizerInfo.cpp 465 if (!MIRBuilder.buildInstr(Opcode)
480 MIRBuilder.buildInstr(Opcode)
492 MIRBuilder.buildInstr(Opcode)
510 MachineInstr *Trap = MIRBuilder.buildInstr(Mips::TRAP);
MipsInstructionSelector.cpp 150 B.buildInstr(Mips::ORi, {DestReg}, {Register(Mips::ZERO)})
156 MachineInstr *Inst = B.buildInstr(Mips::LUi, {DestReg}, {})
163 B.buildInstr(Mips::ADDiu, {DestReg}, {Register(Mips::ZERO)})
169 MachineInstr *LUi = B.buildInstr(Mips::LUi, {LUiReg}, {})
171 MachineInstr *ORi = B.buildInstr(Mips::ORi, {DestReg}, {LUiReg})
604 B.buildInstr(Mips::MTC1, {I.getOperand(0).getReg()}, {GPRReg});
617 MachineInstrBuilder PairF64 = B.buildInstr(
806 MachineInstrBuilder MIB = B.buildInstr(
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMCallLowering.cpp 466 auto CallSeqStart = MIRBuilder.buildInstr(ARM::ADJCALLSTACKDOWN);
533 MIRBuilder.buildInstr(ARM::ADJCALLSTACKUP)

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