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    Searched refs:buildMerge (Results 1 - 14 of 14) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsLegalizerInfo.cpp 410 MIRBuilder.buildMerge(Val, {Load_P2Half, Load_Rem});
412 auto Merge = MIRBuilder.buildMerge(s64, {Load_P2Half, Load_Rem});
439 auto Bitcast = MIRBuilder.buildMerge(s64, {Src, C_HiMask.getReg(0)});
MipsCallLowering.cpp 148 MIRBuilder.buildMerge(ValVReg, {Lo, Hi});
209 MIRBuilder.buildMerge(ArgsReg, VRegs);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
CallLowering.cpp 360 B.buildMerge(OrigRegs[0], Regs);
362 auto Widened = B.buildMerge(LLT::scalar(SrcSize), Regs);
430 auto Merge = B.buildMerge(RealDstEltTy, Regs.take_front(PartsPerElt));
499 UnmergeSrc = B.buildMerge(LCMTy, MergeParts).getReg(0);
LegalizerHelper.cpp 208 MIRBuilder.buildMerge(DstReg, PartRegs);
358 Remerge[I] = MIRBuilder.buildMerge(NarrowTy, SubMerge).getReg(0);
377 MIRBuilder.buildMerge(DstReg, RemergeRegs);
381 auto Remerge = MIRBuilder.buildMerge(LCMTy, RemergeRegs);
395 MIRBuilder.buildMerge(LCMTy, RemergeRegs));
820 MIRBuilder.buildMerge(DstReg, DstRegs);
1050 MIRBuilder.buildMerge(MI.getOperand(0), DstRegs);
1184 MIRBuilder.buildMerge(DstReg, DstRegs);
1204 MIRBuilder.buildMerge(MI.getOperand(0), DstRegs);
1441 auto Merge = MIRBuilder.buildMerge(WideTy, Slicer.take_front(PartsPerGCD))
    [all...]
MachineIRBuilder.cpp 568 buildMerge(Res, Ops);
588 MachineInstrBuilder MachineIRBuilder::buildMerge(const DstOp &Res,
599 MachineIRBuilder::buildMerge(const DstOp &Res,
CombinerHelper.cpp 336 Builder.buildMerge(NewDstReg, Ops);
2224 Builder.buildMerge(DstReg, { Narrowed, Zero });
2237 Builder.buildMerge(DstReg, { Zero, Narrowed });
2247 Builder.buildMerge(DstReg, { Unmerge.getReg(1), Hi });
2253 Builder.buildMerge(DstReg, { Hi, Hi });
2261 Builder.buildMerge(DstReg, { Lo, Hi });
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPULegalizerInfo.cpp 1832 B.buildMerge(Dst, {Src, HighAddr});
1879 auto BuildPtr = B.buildMerge(DstTy, {SrcAsInt, ApertureReg});
2003 auto SignBit64 = B.buildMerge(S64, {Zero32, SignBit});
2079 B.buildMerge(Dst, { Lo, Hi });
2662 auto Merge = B.buildMerge(S32, {Src0, Src1});
2891 auto Rcp = B.buildMerge(S64, {RcpLo, RcpHi});
2906 auto Add1 = B.buildMerge(S64, {Add1_Lo, Add1_Hi});
2919 auto Add2 = B.buildMerge(S64, {Add2_Lo, Add2_Hi});
2933 auto Sub1 = B.buildMerge(S64, {Sub1_Lo, Sub1_Hi});
2956 auto Sub2 = B.buildMerge(S64, {Sub2_Lo, Sub2_Hi})
    [all...]
AMDGPURegisterBankInfo.cpp 933 B.buildMerge(LLT::scalar(64),
988 auto Merge = B.buildMerge(OpTy, ReadlanePieces);
1524 B.buildMerge(Dst, LoadParts);
1666 return B.buildMerge(LLT::vector(NumElts, S32), WideRegs).getReg(0);
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86CallLowering.cpp 383 MIRBuilder.buildMerge(Info.OrigRet.Regs[0], NewRegs);
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
LegalizationArtifactCombiner.h 288 Builder.buildMerge(DstReg, SrcRegs);
689 Builder.buildMerge(DefReg, Regs);
MachineIRBuilder.h 931 MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef<Register> Ops);
932 MachineInstrBuilder buildMerge(const DstOp &Res,
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMCallLowering.cpp 338 MIRBuilder.buildMerge(Arg.Regs[0], NewRegs);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64CallLowering.cpp 410 MIRBuilder.buildMerge({NewLLT}, {CurVReg, Undef}).getReg(0);
AArch64LegalizerInfo.cpp 1142 MIRBuilder.buildMerge(MI.getOperand(0), {DstLo, DstHi});

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