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    Searched refs:buildOr (Results 1 - 6 of 6) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
LegalizerHelper.cpp 1087 MachineInstrBuilder Or = MIRBuilder.buildOr(NarrowTy, XorL, XorH);
1375 MIRBuilder.buildOr(NextResult, ResultReg, Shl);
1877 MIRBuilder.buildOr(OriginalOverflow, Mulo->getOperand(1), Overflow);
1940 MIBSrc = MIRBuilder.buildOr(
2645 return B.buildOr(TargetTy, MaskedOldElt, ShiftedInsertVal).getReg(0);
2772 auto Or = MIRBuilder.buildOr(AnyExtTy, Shift, LargeLoad);
4383 Hi = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
4402 Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
4425 Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
4495 auto HiS = MIRBuilder.buildOr(HalfTy, LoOr, HiOr)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMLegalizerInfo.cpp 455 MIRBuilder.buildOr(OriginalResult, Results[0], Results[1]);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUCallLowering.cpp 860 InputReg = InputReg ? MIRBuilder.buildOr(S32, InputReg, Y).getReg(0) : Y;
869 InputReg = InputReg ? MIRBuilder.buildOr(S32, InputReg, Z).getReg(0) : Z;
AMDGPURegisterBankInfo.cpp 1576 auto MergedInputs = B.buildOr(S32, ClampOffset, ShiftWidth);
2570 auto Or = B.buildOr(S32, ZextLo, ShiftHi);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64PostLegalizerLowering.cpp 945 CmpRes = MIB.buildOr(DstTy, Cmp1Dst, Cmp2Dst).getReg(0);
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
MachineIRBuilder.h 1528 MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0,

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