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    Searched refs:buildPtrAdd (Results 1 - 15 of 15) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsLegalizerInfo.cpp 375 auto Addr = MIRBuilder.buildPtrAdd(PtrTy, BaseAddr, C_P2HalfMemSize);
404 auto Addr = MIRBuilder.buildPtrAdd(PtrTy, BaseAddr, C_P2HalfMemSize);
MipsCallLowering.cpp 271 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64PreLegalizerCombiner.cpp 217 B.buildPtrAdd(
AArch64LegalizerInfo.cpp 992 auto ListTmp = MIRBuilder.buildPtrAdd(PtrTy, List, AlignMinus1.getReg(0));
1005 auto NewList = MIRBuilder.buildPtrAdd(PtrTy, DstPtr, Size.getReg(0));
AArch64CallLowering.cpp 257 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86CallLowering.cpp 101 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
MachineIRBuilder.cpp 182 MachineInstrBuilder MachineIRBuilder::buildPtrAdd(const DstOp &Res,
205 return buildPtrAdd(Res, Op0, Cst.getReg(0));
384 auto Ptr = buildPtrAdd(PtrTy, BasePtr, ConstOffset);
CombinerHelper.cpp 1321 Ptr = MIB.buildPtrAdd(PtrTy, Dst, Offset).getReg(0);
1423 LoadPtr = MIB.buildPtrAdd(PtrTy, Src, Offset).getReg(0);
1429 CurrOffset == 0 ? Dst : MIB.buildPtrAdd(PtrTy, Dst, Offset).getReg(0);
1518 LoadPtr = MIB.buildPtrAdd(PtrTy, Src, Offset).getReg(0);
1535 StorePtr = MIB.buildPtrAdd(PtrTy, Dst, Offset).getReg(0);
2352 auto PtrAdd = Builder.buildPtrAdd(PtrTy, LHS, RHS);
IRTranslator.cpp 1506 BaseReg = MIRBuilder.buildPtrAdd(PtrTy, BaseReg, OffsetMIB.getReg(0))
1533 BaseReg = MIRBuilder.buildPtrAdd(PtrTy, BaseReg, GepOffsetReg).getReg(0);
1540 MIRBuilder.buildPtrAdd(getOrCreateVReg(U), BaseReg, OffsetMIB.getReg(0));
LegalizerHelper.cpp 2766 MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst.getReg(0));
2843 MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst.getReg(0));
3282 return MIRBuilder.buildPtrAdd(PtrTy, VecPtr, Mul).getReg(0);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMCallLowering.cpp 105 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUCallLowering.cpp 205 auto AddrReg = MIRBuilder.buildPtrAdd(PtrTy, SPReg, OffsetReg);
410 B.buildPtrAdd(DstReg, KernArgSegmentVReg, OffsetReg);
AMDGPURegisterBankInfo.cpp 1280 auto PtrAdd = B.buildPtrAdd(PtrTy, SPCopy, ScaledSize);
1284 B.buildPtrAdd(Dst, SPCopy, ScaledSize);
AMDGPULegalizerInfo.cpp 3491 B.buildPtrAdd(DstReg, KernargPtrReg, B.buildConstant(IdxTy, Offset).getReg(0));
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
MachineIRBuilder.h 463 MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0,
477 /// materializePtrAdd() and buildPtrAdd().

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