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    Searched refs:buildSExtInReg (Results 1 - 4 of 4) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
MachineIRBuilder.h 619 MachineInstrBuilder buildSExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPURegisterBankInfo.cpp 1177 B.buildSExtInReg(MI.getOperand(0), WideLoad, MemSize);
1615 auto ExtLo = B.buildSExtInReg(S32, Bitcast, 16);
2392 B.buildSExtInReg(DstRegs[0], SrcRegs[0], Amt);
2399 B.buildSExtInReg(DstRegs[1], DstRegs[0], Amt - 32);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
CombinerHelper.cpp 2995 Builder.buildSExtInReg(MI.getOperand(0).getReg(), Src, Size - ShiftAmt);
LegalizerHelper.cpp 1864 ExtResult = MIRBuilder.buildSExtInReg(WideTy, Mul, SrcBitWidth);
4087 R = MIRBuilder.buildSExtInReg(NarrowTy, R, Imm).getReg(0);

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