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    Searched refs:buildSelect (Results 1 - 6 of 6) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPULegalizerInfo.cpp 1850 B.buildSelect(Dst, CmpRes, PtrLo32, SegmentNull.getReg(0));
1880 B.buildSelect(Dst, CmpRes, BuildPtr, FlatNull);
1907 B.buildSelect(MI.getOperand(0).getReg(), Cond, Src, Tmp2);
1933 auto Add = B.buildSelect(S64, And, One, Zero);
2013 auto Tmp1 = B.buildSelect(S64, ExpLt0, SignBit64, Tmp0);
2014 B.buildSelect(MI.getOperand(0).getReg(), ExpGt51, Src, Tmp1);
2640 CorrectedFract = B.buildSelect(S64, IsNan, ModSrc, Min, Flags).getReg(0);
2825 Q = B.buildSelect(S32, Cond, B.buildAdd(S32, Q, One), Q);
2826 R = B.buildSelect(S32, Cond, B.buildSub(S32, R, Y), R);
2831 B.buildSelect(DstReg, Cond, B.buildAdd(S32, Q, One), Q)
    [all...]
AMDGPURegisterBankInfo.cpp 136 B.buildSelect(DstReg, SrcReg, True, False);
1958 auto S = B.buildSelect(EltTy, Cmp,
2043 auto S = B.buildSelect(EltTy, Cmp, InsRegs[L],
2217 B.buildSelect(DefRegs[0], CondRegs[0], Src1Regs[0], Src2Regs[0]);
2218 B.buildSelect(DefRegs[1], CondRegs[0], Src1Regs[1], Src2Regs[1]);
2498 B.buildSelect(DefRegs[0], SrcReg, True, False);
2501 auto Sel = B.buildSelect(SelType, SrcReg, True, False);
2505 B.buildSelect(DstReg, SrcReg, True, False);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
LegalizerHelper.cpp 1096 MIRBuilder.buildSelect(MI.getOperand(0), CmpHEQ, CmpLU, CmpH);
3107 MIRBuilder.buildSelect(BorrowOut, LHS_EQ_RHS, BorrowIn, LHS_ULT_RHS);
3569 MIRBuilder.buildSelect(DstReg, CondTy.isVector() ? Src0Regs[i] : CondReg,
4501 auto Lo = MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL);
4502 auto Hi = MIRBuilder.buildSelect(
4503 HalfTy, IsZero, InH, MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL));
4529 auto Lo = MIRBuilder.buildSelect(
4530 HalfTy, IsZero, InL, MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL));
4532 auto Hi = MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL);
5111 auto Select = MIRBuilder.buildSelect(NarrowTy
    [all...]
MachineIRBuilder.cpp 764 MachineInstrBuilder MachineIRBuilder::buildSelect(const DstOp &Res,
IRTranslator.cpp 1420 MIRBuilder.buildSelect(ResRegs[i], Tst, Op0Regs[i], Op1Regs[i], Flags);
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
MachineIRBuilder.h 1100 MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst,

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