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    Searched refs:buildUndef (Results 1 - 11 of 11) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPULegalizerInfo.cpp 2130 B.buildUndef(Dst);
2163 B.buildUndef(Dst);
2303 B.buildUndef(DstReg);
3605 PackedRegs.resize(2, B.buildUndef(S32).getReg(0));
3614 PackedRegs.resize(6, B.buildUndef(S16).getReg(0));
3625 PackedRegs.resize(4, B.buildUndef(S32).getReg(0));
4049 B.buildBuildVector(V2S16, {AddrReg, B.buildUndef(S16).getReg(0)})
4083 auto Undef = B.buildUndef(S32);
4150 B.buildUndef(MI.getOperand(0));
4450 Register Undef = B.buildUndef(Ty).getReg(0)
    [all...]
AMDGPURegisterBankInfo.cpp 744 Register InitReg = B.buildUndef(ResTy).getReg(0);
1194 auto Undef = B.buildUndef(LoadTy);
1894 B.buildUndef(Hi32Reg);
AMDGPUCallLowering.cpp 645 B.buildUndef(VRegs[Idx][I]);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
MachineIRBuilder.cpp 573 buildUndef(ResIn);
584 MachineInstrBuilder MachineIRBuilder::buildUndef(const DstOp &Res) {
664 auto UndefVec = buildUndef(DstTy);
CallLowering.cpp 282 Register Undef = B.buildUndef(PartLLT).getReg(0);
494 Register Undef = B.buildUndef(SrcTy).getReg(0);
LegalizerHelper.cpp 223 MIRBuilder.buildUndef(CurResultReg);
295 PadReg = MIRBuilder.buildUndef(GCDTy).getReg(0);
340 AllPadReg = MIRBuilder.buildUndef(NarrowTy).getReg(0);
804 Register ImplicitReg = MIRBuilder.buildUndef(ImplicitTy).getReg(0);
815 DstRegs.push_back(MIRBuilder.buildUndef(NarrowTy).getReg(0));
1308 Register ImpDef = MIRBuilder.buildUndef(OldTy).getReg(0);
1318 Register ImpDef = MIRBuilder.buildUndef(MoreTy).getReg(0);
1431 Register UndefReg = MIRBuilder.buildUndef(GCDTy).getReg(0);
1476 Register Undef = MIRBuilder.buildUndef(WideTy).getReg(0);
3293 auto NewUndef = MIRBuilder.buildUndef(NarrowTy)
    [all...]
CombinerHelper.cpp 202 Undef = Builder.buildUndef(OpType.getScalarType());
235 Builder.buildUndef(NewDstReg);
316 UndefReg = Builder.buildUndef(SrcType).getReg(0);
2767 Builder.buildUndef(MI.getOperand(0));
2841 UndefReg = Builder.buildUndef(DstTy.getScalarType()).getReg(0);
IRTranslator.cpp 2102 MIRBuilder.buildUndef(Undef);
2535 MIRBuilder.buildUndef(Undef);
2896 EntryBuilder->buildUndef(Reg);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64CallLowering.cpp 408 auto Undef = MIRBuilder.buildUndef({OldLLT});
420 auto Undef = MIRBuilder.buildUndef({OldLLT});
AArch64PostLegalizerLowering.cpp 711 auto Undef = B.buildUndef(SrcTy);
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
MachineIRBuilder.h 902 MachineInstrBuilder buildUndef(const DstOp &Res);

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