| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce110/ |
| amdgpu_dce110_clk_mgr.c | 188 context->bw_ctx.bw.dce.all_displays_in_sync;
190 context->bw_ctx.bw.dce.nbp_state_change_enable == false;
192 context->bw_ctx.bw.dce.cpuc_state_change_enable == false;
194 context->bw_ctx.bw.dce.cpup_state_change_enable == false;
196 context->bw_ctx.bw.dce.blackout_recovery_time_us;
209 pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz
215 context->bw_ctx.bw.dce.sclk_khz);
228 = context->bw_ctx.bw.dce.sclk_deep_sleep_khz;
259 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
274 context->bw_ctx.bw.dce.dispclk_khz = dce_set_clock(clk_mgr_base, patched_disp_clk)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_resource.c | 2254 wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];
2265 wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2266 wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2502 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++)
2503 if (context->bw_ctx.dml.vba.NoOfDPP[vlevel][0][pipe_idx] == 1)
2506 if (vlevel > context->bw_ctx.dml.soc.num_states)
2510 context->bw_ctx.dml.vba.maxMpcComb = 0;
2520 if (force_split || context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] > 1)
2533 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx] = dm_odm_combine_mode_2to1
[all...] |
| amdgpu_dcn20_hwseq.c | 1677 &context->bw_ctx.bw.dcn.watermarks,
1690 &context->bw_ctx.bw.dcn.watermarks,
1771 mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| amdgpu_dc_debug.c | 357 context->bw_ctx.bw.dcn.clk.dispclk_khz,
358 context->bw_ctx.bw.dcn.clk.dppclk_khz,
359 context->bw_ctx.bw.dcn.clk.dcfclk_khz,
360 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,
361 context->bw_ctx.bw.dcn.clk.fclk_khz,
362 context->bw_ctx.bw.dcn.clk.socclk_khz);
365 context->bw_ctx.bw.dcn.clk.dispclk_khz,
366 context->bw_ctx.bw.dcn.clk.dppclk_khz,
367 context->bw_ctx.bw.dcn.clk.dcfclk_khz,
368 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz
[all...] |
| amdgpu_dc.c | 1367 memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib));
1793 if (!dc->clk_mgr->funcs->are_clock_states_equal(&dc->clk_mgr->clks, &dc->current_state->bw_ctx.bw.dcn.clk))
1796 } else if (memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_clocks, prev_p_state_change_support)) != 0) {
2503 memcpy(dml, &dc->current_state->bw_ctx.dml, sizeof(struct display_mode_lib));
2510 dc->current_state->bw_ctx.dml = *dml;
2693 info->displayClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dispclk_khz;
2694 info->engineClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_khz;
2695 info->memoryClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dramclk_khz;
2696 info->maxSupportedDppClock = (unsigned int)state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz;
2697 info->dppClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dppclk_khz
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| amdgpu_dce110_resource.c | 958 &context->bw_ctx.bw.dce))
968 if (memcmp(&dc->current_state->bw_ctx.bw.dce,
969 &context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) {
983 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].b_mark,
984 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].a_mark,
985 context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark,
986 context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark,
987 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].b_mark,
988 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].a_mark
[all...] |
| amdgpu_dce110_hw_sequencer.c | 1653 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes],
1654 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes],
1655 context->bw_ctx.bw.dce.stutter_entry_wm_ns[num_pipes],
1656 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes],
1662 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes],
1663 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes],
1664 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes],
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce112/ |
| amdgpu_dce112_resource.c | 879 &context->bw_ctx.bw.dce))
887 if (memcmp(&dc->current_state->bw_ctx.bw.dce,
888 &context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) {
902 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].b_mark,
903 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].a_mark,
904 context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark,
905 context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark,
906 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].b_mark,
907 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].a_mark
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/ |
| amdgpu_dcn_calcs.c | 555 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns =
557 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =
559 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns =
561 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
562 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = v->urgent_watermark * 1000;
569 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns =
571 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =
573 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns =
575 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
576 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = v->urgent_watermark * 1000
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| dce_clk_mgr.c | 232 if (context->bw_ctx.bw.dce.dispclk_khz >
242 < context->bw_ctx.bw.dce.dispclk_khz)
620 context->bw_ctx.bw.dce.all_displays_in_sync;
622 context->bw_ctx.bw.dce.nbp_state_change_enable == false;
624 context->bw_ctx.bw.dce.cpuc_state_change_enable == false;
626 context->bw_ctx.bw.dce.cpup_state_change_enable == false;
628 context->bw_ctx.bw.dce.blackout_recovery_time_us;
630 pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz
635 context->bw_ctx.bw.dce.sclk_khz);
648 = context->bw_ctx.bw.dce.sclk_deep_sleep_khz
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| amdgpu_dcn21_resource.c | 1058 patch_bounding_box(dc, &context->bw_ctx.dml.soc);
1065 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb];
1069 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
1070 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
1072 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_idx];
1078 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
1079 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i]
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn20/ |
| amdgpu_dcn20_clk_mgr.c | 156 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
263 if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
282 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
388 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz;
391 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dispclk_khz;
394 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz;
397 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dppclk_khz;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_hw_sequencer_debug.c | 480 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_khz,
481 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,
482 dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz,
483 dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz,
484 dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz,
485 dc->current_state->bw_ctx.bw.dcn.clk.socclk_khz);
|
| amdgpu_dcn10_hw_sequencer.c | 453 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_khz,
454 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,
455 dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz,
456 dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz,
457 dc->current_state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz,
458 dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz,
459 dc->current_state->bw_ctx.bw.dcn.clk.socclk_khz);
2250 bool should_divided_by_2 = context->bw_ctx.bw.dcn.clk.dppclk_khz <=
2656 context->bw_ctx.bw.dcn.clk.phyclk_khz = 0;
2665 &context->bw_ctx.bw.dcn.watermarks
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce100/ |
| amdgpu_dce_clk_mgr.c | 213 if (context->bw_ctx.bw.dce.dispclk_khz >
223 < context->bw_ctx.bw.dce.dispclk_khz)
406 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce120/ |
| amdgpu_dce120_clk_mgr.c | 96 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce112/ |
| amdgpu_dce112_clk_mgr.c | 204 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn10/ |
| amdgpu_rv1_clk_mgr.c | 137 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce100/ |
| amdgpu_dce100_resource.c | 831 context->bw_ctx.bw.dce.dispclk_khz = 681000;
832 context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ;
834 context->bw_ctx.bw.dce.dispclk_khz = 0;
835 context->bw_ctx.bw.dce.yclk_khz = 0;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| core_types.h | 358 * @bw_ctx: The output from bandwidth and watermark calculations and the DML
370 struct bw_context bw_ctx; member in struct:dc_state
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce80/ |
| amdgpu_dce80_resource.c | 865 context->bw_ctx.bw.dce.dispclk_khz = 681000;
866 context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ;
868 context->bw_ctx.bw.dce.dispclk_khz = 0;
869 context->bw_ctx.bw.dce.yclk_khz = 0;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn21/ |
| amdgpu_rn_clk_mgr.c | 106 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
188 if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
|
