| /src/external/mit/isl/dist/test_inputs/codegen/ |
| separate2.c | 2 for (int c5 = 0; c5 <= 31; c5 += 1)
3 for (int c6 = max(0, 2 * (length % 16) + 2 * c5 - 62); c6 <= 30; c6 += 1) {
4 if (2 * length + c6 >= 2 * (length % 16) + 2 && c6 + 62 >= 2 * (length % 16) + 2 * c5 && 2 * (length % 16) >= c6 + 2 && 2 * (length % 16) + 2 * c5 >= c6 && 2 * (length % 32) + c6 == 2 * (length % 16) + 2 * c5 && (2 * c5 - c6) % 32 == 0)
6 if (length <= 15 && length >= c5 + 1 && c6 >= 1 && length >= c6)
7 S_0(c0, c5, c6 - 1)
[all...] |
| separation_class4.c | 5 for (int c5 = c3 + 58; c5 <= -c3 + 61; c5 += 1)
6 S_0(c3, c5);
10 for (int c5 = max(4 * c0 - c3 + 57, -4 * c0 + c3 + 58); c5 <= min(4 * c0 - c3 + 61, -4 * c0 + c3 + 62); c5 += 1)
11 S_0(c3, c5);
15 for (int c5 = max(-4 * c0 + c3 + 59, 4 * c0 - c3 + 62); c5 <= min(-4 * c0 + c3 + 63, 4 * c0 - c3 + 66); c5 += 1
[all...] |
| lu.c | 7 for (int c5 = max(c2, c3 + 1); c5 <= min(n - 1, c2 + 31); c5 += 1)
8 S_6(c3, c4, c5);
11 for (int c5 = max(c2, c3 + 1); c5 <= min(n - 1, c2 + 31); c5 += 1)
12 S_2(c3, c5);
14 for (int c5 = max(c2, c3 + 1); c5 <= min(n - 1, c2 + 31); c5 += 1
[all...] |
| stride6.c | 3 for (int c5 = max(max(0, -c1 - 1023), niter - c1 - c2 - 32); c5 <= min(min(31, -c1), niter - c1 - c2 - 1); c5 += 1)
4 S_4(niter - 1, -c1 - c5);
|
| shift2.c | 8 for (int c5 = max(0, -c2 + 1); c5 <= min(31, (c3 / 2) - c2 - 1); c5 += 1)
10 S_0(c0, c2 + c5, c3 + c6 - 1);
11 for (int c5 = max(max(0, -c2 + 1), (c3 / 2) - c2); c5 <= min(min(31, length - c2 - 1), (c3 / 2) - c2 + 15); c5 += 1) {
12 for (int c6 = max(0, -c3 + 1); c6 <= min(length - c3, 2 * c2 - c3 + 2 * c5 - 1); c6 += 1)
13 S_0(c0, c2 + c5, c3 + c6 - 1);
14 S_3(c0, 0, c2 + c5);
[all...] |
| correlation.c | 6 for (int c5 = 0; c5 <= min(31, m - c2 - 1); c5 += 1)
7 S_14(c2 + c5);
10 for (int c5 = max(0, c0 - c2 + c3); c5 <= min(31, 2 * c0 - c2 + 2 * c3 - 1); c5 += 1)
11 S_29(-c0 + c2 - c3 + c5, c0 + c3);
14 for (int c5 = 0; c5 <= min(31, 2 * c0 - c2 + 2 * c3 - 1); c5 += 1
[all...] |
| roman.c | 10 for (int c5 = 0; c5 < c3; c5 += 1) {
11 S_16(c1, c3, c5);
12 S_17(c1, c3, c5);
21 for (int c5 = 0; c5 < i + c1 - 2; c5 += 1) {
22 S_16(c1, i + c1 - 2, c5);
23 S_17(c1, i + c1 - 2, c5);
[all...] |
| /src/external/mit/isl/dist/test_inputs/codegen/omega/ |
| ts1d-mp-i_ts-m_b-0.c | 14 for (int c5 = max(0, -N - 500 * c1 + c4 + 2); c5 <= min(min(T - 500 * c1 - 1, -500 * c1 + c4 - 1), -500 * c1 - 2000 * c3 + (c4 + 1) / 2 + 1999); c5 += 1)
15 s1(2, 500 * c1 + c5, 1, -500 * c1 + c4 - c5, 1);
21 for (int c5 = max(0, -N - 500 * c1 + c4 + 2); c5 <= min(min(499, T - 500 * c1 - 1), -500 * c1 + c4 - 1); c5 += 1)
22 s3(2, 500 * c1 + c5, 1, -500 * c1 + c4 - c5, 1)
[all...] |
| lefur04-0.c | 5 for (int c5 = max(max(max(max(0, 2 * c3 - 4), c1 - (-c1 + 3) / 3), c2 - (c2 + 3) / 3), c3 - (c3 + 3) / 3); c5 <= min(min(c1 + 1, c3), -c2 + 2 * c3 - (c2 + 3) / 3 + 2); c5 += 1)
6 for (int c6 = max(max(max(max(max(-200 * c1 + 400 * c3 - 199, 250 * c3 + 1), 1000 * c0 - 500 * c5 - 501), 667 * c0 - 333 * c1 - (c0 + c1 + 3) / 3 - 332), 333 * c1 + c1 / 3), 333 * c2 + (c2 + 1) / 3); c6 <= min(min(min(min(min(min(1000, 500 * c0 + 499), -200 * c1 + 400 * c3 + 400), 500 * c5 + 501), 1000 * c0 - 500 * c5 + 997), 333 * c2 - (-c2 + 3) / 3 + 333), 333 * c3 - (-c3 + 3) / 3 + 334); c6 += 1)
7 for (int c7 = max(max(max(max(500 * c5 + 2, c6), 1000 * c0 - c6), 1000 * c3 - 2 * c6 + 2), 500 * c1 + (c6 + 1) / 2); c7 <= min(min(min(min(500 * c5 + 501, 2 * c6 + 1), 1000 * c0 - c6 + 999), 1000 * c3 - 2 * c6 + 1001), 500 * c1 + (c6 + 1) / 2 + 499); c7 += 1)
8 s0(c0, c1, c2, c3, c2 / 3, c5, c6, c7);
|
| lefur03-0.c | 6 for (int c5 = max(max(max(c4, 1000 * c0 - c4), 1000 * c3 - 2 * c4 + 2), 500 * c1 + (c4 + 1) / 2); c5 <= min(min(min(2 * c4 + 1, 1000 * c0 - c4 + 999), 1000 * c3 - 2 * c4 + 1001), 500 * c1 + (c4 + 1) / 2 + 499); c5 += 1)
7 s0(c0, c1, c2, c3, c4, c5);
|
| /src/sys/arch/arm/arm/ |
| cpufunc_asm_arm10.S | 43 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
47 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
53 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
56 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
|
| cpufunc_asm_arm11x6.S | 67 mcr p15, 0, Rtmp1, c7, c5, 0 /* Invalidate Entire I cache */
81 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
82 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
83 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
84 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
132 mcr p15, 0, r0, c7, c5, 4 /* Flush Prefetch Buffer */
150 mcr p15, 0, r3, c7, c5, 4 /* flush prefetch buffer */
153 mcrr p15, 0, r1, r0, c5 /* invalidate I-cache range */
182 mcr p15, 0, r3, c7, c5, 4 /* flush prefetch buffer */
185 mcrr p15, 0, r1, r0, c5 /* invalidate I-cache range *
[all...] |
| cpufunc_asm_arm67.S | 59 mcrne p15, 0, r0, c5, c0, 0
74 mcr p15, 0, r0, c5, c0, 0
102 mcr p15, 0, r0, c5, c0, 0
|
| cpufunc_asm_armv6.S | 52 mcrne p15, 0, r0, c7, c5, 0 /* Flush I cache */
71 mcrr p15, 0, r1, r0, c5 /* invalidate I cache range */
84 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
126 mcrr p15, 0, r1, r0, c5 /* invalidate I cache range */
139 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
|
| cpufunc_asm_sa1.S | 67 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
78 mcrne p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
96 mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */
100 mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */
114 mcr p15, 0, r0, c7, c5, 0 /* flush I cache */
198 mcr p15, 0, r0, c7, c5, 0 /* flush I cache (D cleaned below) */
217 mcr p15, 0, r0, c7, c5, 0 /* flush I cache */
268 mcr p15, 0, r0, c7, c5, 0 /* flush I cache */
304 mcr p15, 0, r0, c7, c5, 0 /* flush I cache */
|
| cpufunc_asm_armv4.S | 53 mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */
|
| cpufunc_asm_xscale.S | 122 mcrne p15, 0, r0, c7, c5, 6 /* Invalidate the BTB */
150 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
167 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
188 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
192 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
206 mcr p15, 0, r0, c7, c5, 0 /* flush I cache */
216 mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */
323 mcr p15, 0, r0, c7, c5, 0 /* flush I cache (D cleaned below) */
372 mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */
422 mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry *
[all...] |
| cpufunc_asm_arm9.S | 64 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
68 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
92 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
107 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
194 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
209 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
|
| cpufunc_asm_armv5_ec.S | 64 mcr p15, 0, r0, c7, c5, 0 /* Invalidate ICache */
90 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
105 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
187 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
202 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
|
| cpufunc_asm_arm11.S | 93 mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */
103 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
106 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
|
| /src/external/gpl3/gdb.old/dist/gdb/testsuite/gdb.dwarf2/ |
| dw2-multiple-debug-info.c | 25 const int c5 = 5; variable
|
| /src/external/gpl3/gdb/dist/gdb/testsuite/gdb.dwarf2/ |
| dw2-multiple-debug-info.c | 25 const int c5 = 5; variable
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/volt/ |
| gk20a.h | 34 int c5; member in struct:cvb_coef
|
| /src/sys/arch/shark/stand/ofwboot/ |
| srt0.S | 72 mcr p15, 0, r0, c7, c5, 0 /* flush I$ */
|
| /src/external/gpl3/gdb.old/dist/gdb/testsuite/gdb.base/ |
| max-depth.c | 213 struct C5 : C4 { int c5 = 5; } c5; variable in typeref:struct:C4
214 struct C6 : C5 { int c6 = 6; } c6;
|
