| /src/sys/arch/arm/arm/ |
| cpufunc_asm_arm1136.S | 40 mcr p15, 0, r0, c7, c10, 2 /* clean data cache line (via index) */
41 mcr p15, 0, r0, c7, c10, 5 /* data memory barrier */
42 mcr p15, 0, r0, c7, c0, 4 /* wait for interrupt */
|
| cpufunc_asm_arm8.S | 80 mcrne p15, 0, r0, c7, c7, 0 /* flush I+D cache */
86 mcrne p15, 0, r0, c8, c7, 0
89 mcrne p15, 0, r0, c7, c7, 0
103 mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */
108 mcr p15, 0, r0, c8, c7, 1 /* flush I+D tlb single entry */
111 mcr p15, 0, r0, c8, c7, 1 /* flush I+D tlb single entry */
120 mcr p15, 0, r0, c7, c7, 0 /* flush I+D cache *
[all...] |
| cpufunc_asm_armv6.S | 52 mcrne p15, 0, r0, c7, c5, 0 /* Flush I cache */
53 mcrne p15, 0, r0, c7, c14, 0 /* clean and invalidate D cache */
55 mcrne p15, 0, r0, c7, c10, 4 /* drain the write buffer */
59 mcrne p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
73 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
84 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
85 mcr p15, 0, r0, c7, c10, 0 /* Clean D cache */
86 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
95 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
104 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer *
[all...] |
| cpufunc_asm_arm11x6.S | 70 mcr p15, 0, Rtmp1, c7, c5, 0 /* Invalidate Entire I cache */
84 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
85 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
86 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
87 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
105 mcr p15, 0, reg, c7, c14, 0;/* Clean and Invalidate Entire Data Cache */ \
106 mcr p15, 0, reg, c7, c10, 4;/* Data Synchronization Barrier */
110 mcr p15, 0, reg, c7, c14, 0;/* Clean and Invalidate Entire Data Cache */ \
111 mrc p15, 0, reg, c7, c10, 6;/* Read Cache Dirty Status Register */ \
114 mcr p15, 0, reg, c7, c10, 4;/* Data Synchronization Barrier *
[all...] |
| cpufunc_asm_arm11.S | 54 mcrne p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
55 mcrne p15, 0, r0, c7, c10, 4 /* drain write buffer */
71 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
77 mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */
94 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
110 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
117 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
132 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
138 mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */
139 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer *
[all...] |
| cpufunc_asm_sa1.S | 67 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
68 mcr p15, 0, r0, c7, c10, 4 /* drain write and fill buffer */
75 mcrne p15, 0, r0, c8, c7, 0 /* invalidate I+D TLB */
78 mcrne p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
109 mcr p15, 0, r0, c7, c7, 0 /* flush I+D cache */
114 mcr p15, 0, r0, c7, c5, 0 /* flush I cache */
119 mcr p15, 0, r0, c7, c6, 0 /* flush D cache */
124 mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */
129 mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry *
[all...] |
| cpufunc_asm_xscale.S | 122 mcrne p15, 0, r0, c7, c5, 6 /* Invalidate the BTB */
150 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
151 mcr p15, 0, r0, c7, c10, 4 /* drain write and fill buffer */
164 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLB */
167 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
201 mcr p15, 0, r0, c7, c7, 0 /* flush I+D cache */
206 mcr p15, 0, r0, c7, c5, 0 /* flush I cache */
211 mcr p15, 0, r0, c7, c6, 0 /* flush D cache */
216 mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry *
[all...] |
| cpufunc_asm_armv5_ec.S | 64 mcr p15, 0, r0, c7, c5, 0 /* Invalidate ICache */
65 2: mrc p15, 0, APSR_nzcv, c7, c14, 3 /* Test, clean and invalidate DCache */
67 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
71 mcrne p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
90 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
91 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
95 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
105 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
110 mrc p15, 0, APSR_nzcv, c7, c10, 3 /* Test and clean (don't invalidate) */
112 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer *
[all...] |
| cpufunc_asm_armv5.S | 56 mcrne p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
79 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
80 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
84 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
94 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
103 mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */
107 mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */
110 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
127 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
131 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer *
[all...] |
| cpufunc_asm_arm67.S | 53 mcrne p15, 0, r2, c7, c0, 0
62 mcrne p15, 0, r0, c7, c0, 0
85 mcr p15, 0, r0, c7, c0, 0
96 mcr p15, 0, r0, c7, c0, 0 /* flush cache */
106 mcr p15, 0, r0, c7, c0, 0 /* flush cache */
|
| cpufunc_asm_arm7tdmi.S | 83 mcr p15, 0, r0, c8, c7, 0
88 mcr p15, 0, r0, c8, c7, 1
91 mcr p15, 0, r0, c8, c7, 1
102 mcr p15, 0, r0, c7, c7, 0
|
| cpufunc_asm_arm9.S | 55 mcrne p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
92 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
93 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
107 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
116 mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */
120 mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */
139 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
156 mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
177 mcr p15, 0, r0, c7, c6, 1 /* Invalidate D cache SE with VA */
194 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA *
[all...] |
| cpufunc_asm_arm10.S | 73 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
75 mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */
|
| cpufunc_asm_armv4.S | 47 mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */
76 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
|
| cpufunc_asm_ixp12x0.S | 57 mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */
|
| cpufunc_asm_armv7.S | 59 mcr p15, 0, r0, c8, c7, 0 @ flush the I+D
68 mcr p15, 0, r0, c8, c7, 2 @ flush I+D tlb all ASID
88 mcr p15, 0, r0, c8, c7, 1 @ flush I+D tlb single entry
91 mcr p15, 0, r0, c8, c7, 1 @ flush I+D tlb single entry
129 mcr p15, 0, r0, c8, c7, 0 @ flush entire I+D tlb
130 mcr p15, 0, r0, c7, c5, 6 @ branch predictor invalidate
142 mcr p15, 0, r0, c7, c1, 6 @ branch predictor invalidate, IS
159 mcr p15, 0, r0, c8, c7, 0 @ invalidate all I+D TLBs
194 mcr p15, 0, r0, c7, c10, 1 @ wb the D-Cache line
195 mcr p15, 0, r0, c7, c5, 1 @ invalidate the I-Cache lin
[all...] |
| cpufunc_asm_sa11x0.S | 116 mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */
|
| cpufunc_asm_sheeva.S | 78 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
120 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
162 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
198 mcr p15, 0, r0, c7, c5, 1
211 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
257 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
301 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
345 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
354 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
363 mcr p15, 0, r0, c7, c0, 4 /* wait for interrupt *
[all...] |
| /src/sys/arch/shark/stand/ofwboot/ |
| srt0.S | 71 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
72 mcr p15, 0, r0, c7, c5, 0 /* flush I$ */
|
| /src/sys/arch/acorn32/stand/boot32/ |
| start.S | 80 mcreq p15, 0, r0, c7, c0, 0 /* flush v3 ID cache */
81 mcrne p15, 0, r0, c7, c7, 0 /* flush v4 ID cache */
82 mcrne p15, 0, r0, c7, c10, 4 /* drain WB (v4) */
96 /*1*/ mcrne p15, 0, r1, c7, c5, 0 /* write zero in ARMv4 MMU disable */
135 mcreq p15, 0, r0, c7, c0, 0 /* flush v3 ID cache */
136 mcrne p15, 0, r0, c7, c7, 0 /* flush v4 ID cache */
141 mcrne p15, 0, r0, c7, c10, 4 /* drain WB (v4) */
|
| /src/sys/arch/evbarm/ixm1200/ |
| ixm1200_start.S | 87 mrc p15, 0, r0, c7, c7 ,0 /* flush D and I cache */
88 mrc p15, 0, r0, c7, c10 ,4 /* drain write buffer */
91 mcr p15, 0, r0, c8, c7 ,0 /* flush D and I TLB */
154 mcr p15, 0, r0, c8, c7 ,0 /* flush D and I TLB */
|
| /src/common/lib/libc/arch/arm/atomic/ |
| atomic_op_asm.h | 81 #define DMB mcr p15, 0, r0, c7, c10, 5 /* Data Memory Barrier */
|
| /src/sys/arch/evbarm/viper/ |
| viper_start.S | 178 mcr p15, 0, r3, c7, c10, 2
184 mcr p15, 0, r6, c7, c10, 4
227 mcr p15, 0, r3, c7, c10, 2
233 mcr p15, 0, r6, c7, c10, 4
236 mcr p15, 0, r0, c8, c7, 0
|
| /src/sys/arch/evbarm/marvell/ |
| marvell_start.S | 222 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */
228 mcreq p15, 0, r0, c8, c7, 0 /* Flush TLB */
231 mcr p15, 0, r0, c7, c6, 0 /* Invalidate D cache */
232 mcr p15, 0, r0, c7, c10, 4 /* Drain write-buffer */
|
| /src/sys/arch/evbarm/gemini/ |
| gemini_start.S | 199 mcr p15, 0, r0, c7, c5, 0 /* Invalidate Entire I cache */
200 mcr p15, 0, r0, c7, c14, 0 /* Clean & Invalidate Entire D cache */
209 mcr p15, 0, r0, c7, c5, 6 /* invalidate BTB all */
210 mcr p15, 0, r0, c7, c10, 4 /* Drain the write buffers. */
212 mcr p15, 0, r0, c8, c7, 0 /* Invalidate TLBs */
|
