| /src/sys/arch/aarch64/aarch64/ |
| cpufunc.c | 135 int cacheable; local
139 cacheable = CACHE_CACHEABLE_NONE;
142 cacheable = CACHE_CACHEABLE_ICACHE;
146 cacheable = CACHE_CACHEABLE_DCACHE;
150 cacheable = CACHE_CACHEABLE_IDCACHE;
155 cacheable = CACHE_CACHEABLE_UNIFIED;
159 cacheable = CACHE_CACHEABLE_NONE;
163 cinfo[level].cacheable = cacheable;
164 if (cacheable == CACHE_CACHEABLE_NONE)
227 const char *cacheable, *cachetype; local
[all...] |
| /src/sys/arch/emips/emips/ |
| bus_space.c | 54 int cacheable = flags & BUS_SPACE_MAP_CACHEABLE; local
57 if (cacheable)
|
| /src/sys/arch/pmax/pmax/ |
| bus_space.c | 49 int cacheable = flags & BUS_SPACE_MAP_CACHEABLE; local
52 if (cacheable)
|
| /src/sys/arch/arc/arc/ |
| bus_space_sparse.c | 76 const bool cacheable = (flags & BUS_SPACE_MAP_CACHEABLE) != 0; local
77 const u_int pmap_flags = cacheable ? PMAP_WRITE_BACK : 0;
88 *bshp = (cacheable ?
|
| /src/sys/arch/arm/footbridge/ |
| footbridge_com_io.c | 139 fcomcons_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int cacheable, bus_space_handle_t *bshp)
158 int cacheable,
|
| footbridge_io.c | 166 footbridge_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int cacheable, bus_space_handle_t *bshp)
250 int cacheable,
|
| /src/sys/arch/arm/iomd/ |
| iomd_io.c | 134 iomd_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int cacheable,
149 bus_size_t alignment, bus_size_t boundary, int cacheable, bus_addr_t *bpap,
|
| /src/sys/arch/cesfic/cesfic/ |
| autoconf.c | 105 mainbus_map(u_long physaddr, int size, int cacheable, void ** virtaddr)
126 if (!cacheable) {
|
| /src/sys/arch/acorn32/podulebus/ |
| podulebus_io.c | 133 podulebus_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int cacheable, bus_space_handle_t *bshp)
147 int cacheable, bus_addr_t *bpap, bus_space_handle_t *bshp)
|
| /src/sys/arch/arm/at91/ |
| at91_bus_space.c | 137 int cacheable, bus_space_handle_t *bshp)
198 bus_size_t size, bus_size_t alignment, bus_size_t boundary, int cacheable,
|
| /src/sys/arch/arm/clps711x/ |
| clps711x_space.c | 128 int cacheable, bus_space_handle_t *bshp)
183 bus_size_t alignment, bus_size_t boundary, int cacheable,
|
| /src/sys/arch/arm/ep93xx/ |
| ep93xx_space.c | 132 int cacheable, bus_space_handle_t *bshp)
193 bus_size_t size, bus_size_t alignment, bus_size_t boundary, int cacheable,
|
| /src/sys/arch/arm/footbridge/isa/ |
| isa_io.c | 249 isa_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int cacheable, bus_space_handle_t *bshp)
278 int cacheable,
|
| /src/sys/arch/arm/xscale/ |
| ixp425_space.c | 133 int cacheable, bus_space_handle_t *bshp)
194 bus_size_t size, bus_size_t alignment, bus_size_t boundary, int cacheable,
|
| ixp425_pci_space.c | 225 int cacheable, bus_space_handle_t *bshp)
239 bus_size_t size, bus_size_t alignment, bus_size_t boundary, int cacheable,
439 bus_size_t size, bus_size_t alignment, bus_size_t boundary, int cacheable,
|
| /src/sys/arch/vax/vax/ |
| bus_mem.c | 49 int cacheable,
|
| /src/sys/arch/evbarm/ifpga/ |
| ifpga_io.c | 240 ifpga_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int cacheable, bus_space_handle_t *bshp)
248 ifpga_mem_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int cacheable, bus_space_handle_t *bshp)
277 /* XXX pmap_kenter_pa maps pages cacheable -- not what
291 bus_size_t alignment, bus_size_t boundary, int cacheable,
|
| /src/sys/arch/hpcmips/hpcmips/ |
| bus_space.c | 247 bus_size_t size, int cacheable)
253 mips_pte_cachechange, cacheable); local
257 return cacheable ? MIPS_PHYS_TO_KSEG0(bpa) : MIPS_PHYS_TO_KSEG1(bpa);
267 int cacheable = flags & BUS_SPACE_MAP_CACHEABLE; local
285 *bshp = __hpcmips_cacheable(t, bpa, size, cacheable);
332 int cacheable = flags & BUS_SPACE_MAP_CACHEABLE; local
349 *bshp = __hpcmips_cacheable(t, bpa, size, cacheable);
|
| bus_space_through.c | 44 bus_size_t size, int cacheable, bus_space_handle_t *bshp)
46 return bus_space_map(t->bs_base, addr, size, cacheable, bshp);
68 bus_size_t size, bus_size_t align, bus_size_t boundary, int cacheable,
72 cacheable, addrp, bshp);
|
| /src/sys/arch/evbarm/tsarm/isa/ |
| isa_io.c | 296 isa_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int cacheable, bus_space_handle_t *bshp)
335 int cacheable,
|
| /src/sys/arch/shark/isa/ |
| isa_io.c | 339 isa_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int cacheable, bus_space_handle_t *bshp)
399 bus_size_t alignment, bus_size_t boundary, int cacheable,
|
| /src/sys/arch/m68k/m68k/ |
| bus_dma.c | 132 int seg, cacheable, coherent = BUS_DMA_COHERENT; local
149 rv = pmap_extract_info(pmap, vaddr, &curaddr, &cacheable);
151 cacheable = !(cacheable & PMAP_NOCACHE);
155 cacheable = _pmap_page_is_cacheable(pmap, vaddr);
158 if (cacheable)
186 cacheable ? 0 : BUS_DMA_COHERENT;
203 cacheable ? 0 : BUS_DMA_COHERENT;
|
| /src/sys/arch/arm/mainbus/ |
| mainbus_io.c | 214 int cacheable,
|
| /src/sys/arch/arm/sa11x0/ |
| sa11x0_io.c | 182 bus_size_t alignment, bus_size_t boundary, int cacheable,
|
| /src/sys/arch/aarch64/include/ |
| cpu.h | 91 u_int cacheable; member in struct:aarch64_cache_info
|
