| /src/sys/external/bsd/drm2/dist/drm/amd/amdkfd/ |
| kfd_topology.h | 125 uint32_t cacheline_size; member in struct:kfd_cache_properties
|
| kfd_crat.c | 326 props->cacheline_size = cache->cache_line_size;
|
| kfd_topology.c | 352 sysfs_show_32bit_prop(buffer, "cache_line_size", cache->cacheline_size);
|
| /src/sys/dev/pci/ |
| pciconf.c | 158 int cacheline_size; member in struct:_s_pciconf_bus_t
408 pb->cacheline_size = parent->cacheline_size;
1348 misc |= ((pb->cacheline_size >> 2) & PCI_CACHELINE_MASK) <<
1547 int firstbus, int cacheline_size)
1556 pb->cacheline_size = cacheline_size;
|
| /src/sys/dev/marvell/ |
| gtpci.c | 444 int cacheline_size)
460 GTPCI_P2PC_BUSNUMBER(p2pc), cacheline_size);
|
| mvpex.c | 408 int cacheline_size)
424 MVPEX_STAT_PEXBUSNUM(stat), cacheline_size);
|
| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| intel_pm.c | 567 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
575 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
583 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
591 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
599 .cacheline_size = I915_FIFO_LINE_SIZE,
607 .cacheline_size = I915_FIFO_LINE_SIZE,
615 .cacheline_size = I915_FIFO_LINE_SIZE,
623 .cacheline_size = I830_FIFO_LINE_SIZE,
631 .cacheline_size = I830_FIFO_LINE_SIZE,
639 .cacheline_size = I830_FIFO_LINE_SIZE
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_display_types.h | 1149 u8 cacheline_size; member in struct:intel_watermark_params
|
