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    Searched refs:ccode (Results 1 - 10 of 10) sorted by relevancy

  /src/usr.bin/genassym/
genassym.sh 31 ccode=0 # generate temporary C file, compile it, execute result
46 ccode=1
156 if (ccode)
162 if (ccode)
190 if (ccode) {
197 ' ccode="$ccode" fcode="$fcode" > "${genassym_temp}/assym.c" || exit 1
199 if [ "$ccode" = 1 ]; then
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/broadcom/
bcm4709-netgear-r8000.dts 143 brcm,ccode-map = "JP-JP-78", "US-Q2-86";
173 brcm,ccode-map = "JP-JP-78", "US-Q2-86";
187 brcm,ccode-map = "JP-JP-78", "US-Q2-86";
  /src/bin/csh/
exp.c 400 int ccode, i; local
427 ccode = exp0(vp, ignore);
429 etraci("exp6 () ccode", ccode, vp);
434 return (putn(ccode));
  /src/sys/dev/qbus/
ts.c 577 short ccode = sc->sc_vts->cmd.cmdr & TS_CF_CCODE; local
653 sc->sc_liowf = (ccode == TS_CC_WRITE);
  /src/sys/arch/m68k/060sp/dist/
ilsp.s 208 # it was a divs.l, so ccode setting is a little more complicated...
235 tst.l %d6 # may set 'N' ccode bit
257 ori.w &0x02,DIV64_CC(%a6) # set 'V' ccode bit
614 # save the zero result to the register file and set the 'Z' ccode bit.
622 mov.w %d4,%cc # set 'Z' ccode bit
751 # save the zero result to the register file and set the 'Z' ccode bit.
759 mov.w %d4,%cc # set 'Z' ccode bit
pfpsp.s 3644 # Here, we zero the ccode and exception byte field since we're going to
6876 # bset &z_bit, FPSR_CC(%a6) # yes; set zero ccode bit
6877 bset &z_bit, %d0 # yes; set zero ccode bit
6936 # bset &z_bit,FPSR_CC(%a6) # yes; set zero ccode bit
6937 bset &z_bit,%d0 # yes; set zero ccode bit
8524 bset &neg_bit,FPSR_CC(%a6) # yes, so set 'N' ccode bit
8540 bset &neg_bit,FPSR_CC(%a6) # yes, so set 'N' ccode bit
8642 bset &neg_bit,FPSR_CC(%a6) # set 'N' ccode bit
9300 mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' ccode bit
9321 mov.b &neg_bmask,FPSR_CC(%a6) # yes, set 'N' ccode bi
    [all...]
fpsp.s 3644 # Here, we zero the ccode and exception byte field since we're going to
4081 # clear the ccode byte and exception status byte
7640 mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' ccode bit
7649 mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' ccode bit
7667 mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' ccode bit
10135 # - Set FPSR exception status dz bit, ccode inf bit, and #
10196 bset &neg_bit,FPSR_CC(%a6) # yes; set 'N' ccode bit
10436 mov.b (tbl_unf_cc.b,%pc,%d0.w*1),FPSR_CC(%a6) # insert ccode bits
10501 mov.b &z_bmask,FPSR_CC(%a6) # set 'Z' ccode bit
10508 mov.b &neg_bmask+z_bmask,FPSR_CC(%a6) # set 'N','Z' ccode bit
    [all...]
isp.s 2178 # it was a divs.l, so ccode setting is a little more complicated...
2203 tst.l %d6 # set %ccode bits
2661 # save the zero result to the register file and set the 'Z' ccode bit.
2666 movq.l &0x4, %d7 # set 'Z' ccode bit
2667 bra.b mul64_ccode_set # finish ccode set
fplsp.s 7534 mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' ccode bit
7543 mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' ccode bit
7561 mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' ccode bit
10482 mov.b &z_bmask,FPSR_CC(%a6) # set 'Z' ccode bit
10489 mov.b &neg_bmask+z_bmask,FPSR_CC(%a6) # set 'N','Z' ccode bits
10515 mov.b &inf_bmask,FPSR_CC(%a6) # set 'INF' ccode bit
10524 mov.b &neg_bmask+inf_bmask,FPSR_CC(%a6) # set 'N','I' ccode bits
10592 mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' ccode bit
  /src/sys/dev/
ipmi.c 885 uint8_t cCode;
1057 /* Need three extra bytes: netfn/cmd/ccode + data */
2397 unsigned char ccode, *buf = NULL; local
2483 ccode = (unsigned char)error;
2504 error = copyout(&ccode, recv->msg.data, 1);

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