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    Searched refs:cfg3 (Results 1 - 4 of 4) sorted by relevancy

  /src/sys/arch/mips/mips/
mips_machdep.c 952 const uint32_t cfg3 = mipsNN_cp0_config3_read(); local
953 if (cfg3 & MIPSNN_CFG3_ULRI) {
956 if (cfg3 & MIPSNN_CFG3_DSP2P) {
1098 const uint32_t cfg3 = mipsNN_cp0_config3_read(); local
1099 if (cfg3 & MIPSNN_CFG3_ULRI) {
1102 if (cfg3 & MIPSNN_CFG3_DSP2P) {
  /src/sys/dev/ic/
ncr53c9xvar.h 178 uint8_t cfg3; /* per target config 3 */ member in struct:ncr53c9x_tinfo
361 #define NCR_F_HASCFG3 0x01 /* chip has CFG3 register */
ncr53c9x.c 419 printf("%s: ncr53c9x_reset: cfg1 0x%x, cfg2 0x%x, cfg3 0x%x, "
546 ti->cfg3 = 0;
622 uint8_t cfg3 = sc->sc_cfg3 | ti->cfg3; local
640 cfg3 |= sc->sc_cfg3_fscsi;
648 (cfg3 & NCRAMDCFG3_FSCSI) == 0)
656 NCR_WRITE_REG(sc, NCR_CFG3, cfg3);
1815 ti->cfg3 |= NCRFASCFG3_EWIDE;
rtw.c 464 uint8_t cfg3; local
466 cfg3 = RTW_READ8(regs, RTW_CONFIG3);
467 cfg3 |= RTW_CONFIG3_CLKRUNEN;
469 cfg3 |= RTW_CONFIG3_PARMEN;
471 cfg3 &= ~RTW_CONFIG3_PARMEN;
472 RTW_WRITE8(regs, RTW_CONFIG3, cfg3);

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