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    Searched refs:cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP (Results 1 - 2 of 2) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/nbio/
nbio_7_0_offset.h	1264 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP 0x024c
nbio_2_3_offset.h	1770 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP 0x024c     [all...]

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