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    Searched refs:cfgPSWUSCFG0_MEM_BASE_LIMIT (Results 1 - 2 of 2) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/nbio/
nbio_6_1_offset.h	45 #define cfgPSWUSCFG0_MEM_BASE_LIMIT 0x0020
nbio_7_4_offset.h	45 #define cfgPSWUSCFG0_MEM_BASE_LIMIT 0x0020

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