HomeSort by: relevance | last modified time | path
    Searched refs:cfgcr0 (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_dpll_mgr.c 2047 val = pll->state.hw_state.cfgcr0;
2055 if (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
2165 hw_state->cfgcr0 = val;
2329 u32 cfgcr0, cfgcr1; local in function:cnl_ddi_hdmi_pll_dividers
2332 cfgcr0 = DPLL_CFGCR0_HDMI_MODE;
2337 cfgcr0 |= DPLL_CFGCR0_DCO_FRACTION(wrpll_params.dco_fraction) |
2349 crtc_state->dpll_hw_state.cfgcr0 = cfgcr0;
2357 u32 cfgcr0; local in function:cnl_ddi_dp_set_dpll_hw_state
2359 cfgcr0 = DPLL_CFGCR0_SSC_ENABLE
2623 u32 cfgcr0, cfgcr1; local in function:icl_calc_dpll_state
    [all...]
intel_dpll_mgr.h 193 u32 cfgcr0; member in struct:intel_dpll_hw_state
201 * u32 cfgcr0, cfgcr1;
intel_ddi.c 1421 dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK)
1424 dco_freq += (((pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
1584 if (pll_state->cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1587 link_clock = pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
intel_display.c 13676 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
  /src/sys/external/bsd/drm2/dist/drm/i915/
i915_debugfs.c 2762 seq_printf(m, " cfgcr0: 0x%08x\n", pll->state.hw_state.cfgcr0);

Completed in 31 milliseconds