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    Searched refs:cfgcr1 (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_dpll_mgr.c 963 i915_reg_t ctl, cfgcr1, cfgcr2; member in struct:skl_dpll_regs
976 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1),
982 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2),
988 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3),
1018 I915_WRITE(regs[id].cfgcr1, pll->state.hw_state.cfgcr1);
1020 POSTING_READ(regs[id].cfgcr1);
1080 hw_state->cfgcr1 = I915_READ(regs[id].cfgcr1);
1372 u32 ctrl1, cfgcr1, cfgcr2 local in function:skl_ddi_hdmi_pll_dividers
2329 u32 cfgcr0, cfgcr1; local in function:cnl_ddi_hdmi_pll_dividers
2623 u32 cfgcr0, cfgcr1; local in function:icl_calc_dpll_state
    [all...]
intel_dpll_mgr.h 190 u32 cfgcr1, cfgcr2; member in struct:intel_dpll_hw_state
194 /* CNL also uses cfgcr1 */
201 * u32 cfgcr0, cfgcr1;
intel_ddi.c 1365 dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK)
1368 dco_freq += (((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9)
1382 p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1383 p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
1385 if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1386 p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
intel_display.c 13674 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
  /src/sys/external/bsd/drm2/dist/drm/i915/
i915_debugfs.c 2763 seq_printf(m, " cfgcr1: 0x%08x\n", pll->state.hw_state.cfgcr1);

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